TW200412096A - Software defined radio (SDR) architecture for wireless digital communication systems - Google Patents

Abstract

A system and method for providing one hardware platform to implement multiple wireless communication standards, services and applications. The kernel-oriented macro-based software defined radio(SDR) multi-layered architecture provides a configurable and programmable hardware platform to implement multiple wireless communication standards, services and applications.

Description

200412096

[Technical field to which the invention belongs] The present invention relates to a wireless digital communication, and more particularly, to a wireless technology that can use a multi-layered (mul ti-layered) architecture to implement wireless communication standards, services, and applications. Digital "software defined radio" (SDR) architecture of digital communication systems. [Previous technology] Generally speaking, bandwidth is an expensive resource, and many countries regard bandwidth as a general asset. Because different regions The different usage of the released frequency bands for different communication services makes it difficult for the equipment in Area A to communicate with the equipment in Area B. Typically, the wireless communication standard will be implemented on different ^ hedron platforms. Mode global mobile communication system_ (globe system for mobile communication, GSM) Outside of mobile phones, mobile phones that can communicate in the GSM area of 900 MHz will not be able to communicate in the area of 1 800 Μ Η z GS Μ. When used When the user moves in different regions, the user will not be able to use the services provided by the vendors in different regions for mobile phone communication. Therefore When the user moves from one area to another, the user must carry a constant type of mobile phone with different communication specifications in order to use different mobile phones with different communication specifications for communication in different areas, which is quite inconvenient. Please refer to Figure 1 'The drawing is a block diagram of a general wireless digital communications system 1 ο 〇 used to implement a single communication standard. In Figure 1, first, the antenna I_ 102 (antenna) will receive the external signal, and then the radio frequency (radio frequency, RF) subsystem ι〇4 and intermediate frequency

200412096 V. Description of the invention (2) (intermediate frequency (I / F)) subsystem 106 will sequentially receive this signal and perform analog signal processing first. Among them, the RF subsystem 104 and the I / F subsystem 106 are used to execute waveform processing procedures of analog signals. The processing procedures include mixing, filtering, amplifying, and amplifying control of analog signals. Then, the analog-to-digital converter (A / D) subsystem 108 receives analog signals that have been processed by the RF subsystem 104 and the I / F subsystem 106, and A The / D subsystem 108 converts the received analog signal into an equivalent digital signal.

Next, the dedicated logic element 11 will receive and process the digital signals output by the A / D subsystem 1 08 to perform the functions of the stand-specific and the channel 1 (spec ific). , Such as modem functions, digital filtering functions, and other proprietary signal processing functions. Then, the dedicated logic element 1 1 〇 transmits the processed signal to the programmable logic element 11 through a bus 11 2, a digital signal processor (DSP) 116 and a microprocessor 1 1 8. By controlling the configuration and functions of the programmable logic element 11 4 and downloading and managing the data flow input and output of the programmable logic element n 4, new specific functions can also be performed. For applications requiring lower processing speeds, DSP 1 1 6 can perform digital signal (s i gna 1 i ng) processing functions. For applications that require higher processing speed, the programmable logic element UI 4 can provide specific specialized hardware solutions to perform the most common requirements for digital signal processing. Microprocessor 1 1 8 series general purpose microprocessor and used

TW724PA (工 硏 院 __ 电 通 所) .ptd Page 6 200412096 V. Description of the invention (3) | Executive control function. Please refer to Figure 1 again. The software part 12 0 shows the control structure of a traditional single communication standard device. Operating system (OS) 122 plays the role of program management and operates on the microprocessor u 8. The application program 24 can perform hardware / software j function settings and operates under 〇 122. Because the application program 124 needs computing resources, the 'programmable logic element 11 4, DSP 11 6 and microprocessor etc. must be used to perform signal processing and generate data flow and control flow. By combining these resources, applications 1 2 4 will be able to operate on hardware platforms, and achieve the required performance. Please refer to FIG. 2, which shows a block diagram for implementing one of the multiple communication standards. The wireless digital communication system 2000. The architecture of the wireless digital communication system 2000 in FIG. 2 is similar to the structure of the wireless digital communication system 1 in FIG. 1, but the difference is that the wireless digital communication system 2 in FIG. 2 has A dedicated logic component bank (bank) 202 is used to provide different specific standard functions, specific channel functions, specific modem functions, and other signal | processing functions. In the second figure, first, the antenna 102 will receive the external signal, and then, the RF subsystem 104 and the I / F subsystem 106 will receive this signal and perform the processing first. The A / D subsystem 108 will then receive analog signals that have been processed by the RF subsystem 104 and the I / F subsystem 106. Next, the dedicated logic element library 202 will receive the digital signals output by the A / D subsystem 108. Then, the dedicated logic element library 202 will transmit the processed signals to the programmable logic element 114, DSP 116, and microprocessor 118 through the bus 11 2. Typically, a dedicated logic TW0724PA (Industrial and Industrial Research Institute_Telecommunications Institute) .ptd Page 7 200412096

The component library 2 0 2 is a standard for different wireless digital communications. Therefore, the method described in Section 2 that can generally provide multiple communication standards is basically optimized by combining the hardware and software resources required by the optimized standard. Therefore, this platform has a poor efficiency in terms of size, cost and power consumption. Please refer to FIG. 3, which shows a block diagram of a control architecture 300 of a general multi-standard communication device, that is, FIG. 3 is a diagram of resource management of the wireless digital communication system 2000 of FIG. In Fig. 3, os 2 22 plays the role of program management and can be executed on the microprocessor 11 8 in Fig. 2. Therefore, each application 1 2 4 that can perform the setting of the hardware / software function can run under the OS 1 2 2. The resource requirements for applications 12 and services are different for different standards. Since each application program 1 2 4 needs computing resources, so either the programmable logic element 11 4 and DSP 1 1 6 provide signal processing and establish data flow and control flow, or the microprocessor 11 8 provides signal processing and Establish data flow and control flow. Different products and services will determine the required resources and combine resources. After proper combination, each application 1 2 4 can operate on the hardware platform and achieve the required performance. Obviously, the control architecture 300 has poor efficiency in terms of size, cost, and power consumption. Please refer to Figure 4, which shows the relative relationship between the efficiency and elasticity (f 1 e X i b i 1 i t y) presented by different hardware. In Figure 4, from the point of view of efficiency, efficiency is in order from special to integrated circuit (application-specific integrated circuit (ASIC), DSP, embedded processor, and field programmable gate Array (fie 1 d

200412096 V. Description of the invention (5) programmable gate array5 FPGA). Among them, AS I C has higher efficiency because fixed hardware resources such as ASIC tend to design for special functions. Generally speaking, highly configurable and programmable logic units such as microprocessors and digital signal processors have lower efficiency chip sizes and functions. By analyzing the millions of operations per milliWatt (MOPS / mW) of these operational logic elements and knowing their energy efficiency distribution among each other, we can find the AS 1C and DSP in Figure 4 There is an efficiency gap between them. Please refer to FIG. 5, which shows a block diagram of a wireless digital communication device 500. In Figure 5, the wireless digital communication device 500 includes a digital frequency down-converter (DDC) 518, a digital frequency up-converter (DUC) 519, and a programmable Digital Signal Processor (DSP) 5 0 2, Programmable Microprocessor (// P) 504, Heterogeneous re-configurable (heterogeneous re-configurable) multi-processing logic circuit 50 6 and Bus 508. Among them, ‘Bus 5 0 8 is used to provide a programmable digital signal processor 502, a programmable microprocessor 504, and a heterogeneous reconfigurable multiple processing logic circuit 506. Heterogeneous reconfigurable multiprocessing logic circuit 5 〇6 includes heterogeneous signal processing core 5 1 0, programmable digital signal processing core 5 1 2 and programmable microprocessing core 5 1 4 A stateful data router (not shown in Figure 5), and a reconfigurable data router is used to provide electrical connection to a heterogeneous signal processing core 5 丨 〇. In addition, the programmable microprocessor 504 will control the reconfigurable data router and heterogeneous signal processing core via several control buses (not shown in the figure).

Page? 00412096 V. Description of the invention (6) 510. The platform built in the wireless digital communication device 5 0 0 will enable the platform resources to be reconfigured, and provide more flexibility in calculation and control operations through the use of heterogeneous reconfigurable multi-processing logic circuits 5 6 use. The wireless digital communication device 500 is built according to software modules, and each software module is integrated with hardware. Heterogeneous signal processing core 5 1 0, programmable digital signal processing core 5 1 2 and programmable microprocessor core 5 1 4 series can be executed separately in heterogeneous reconfigurable multiprocessing logic circuit 5 0 6, programmable The programmable digital signal processor 502 and the programmable microprocessor 504. The executable code 5 1 6 is the management of the input and output of the data flow of the heterogeneous reconfigurable multiple processing logic circuit 506, and controls the data flow and control flow of all computing resources. When the wireless digital communication device 500 is a component that provides efficient fixed hardware resources like AS IC and retains reconfigurable flexibility, the wireless digital communication device 500 can be used according to different needs. Reconfigure to a different hardware. To achieve multiple standards, applications, and services, heterogeneous reconfigurable multiprocessing logic circuits 506 provide a solution to the contradiction between improved computing efficiency and architectural flexibility. However, in the wireless digital communication device 500, the locality of the reconfigurable data router and the required memory on the bus structure (not shown in Figure 5) will limit the wireless digital communication device 500 Upgrade space and reach. [Summary] In view of this, the object of the present invention is to provide a wireless digital communication

TW724PA (Industrial and Electrical Engineering Institute-Telecommunications Institute) .ptd Page 10 200412096 V. Description of the Invention (7) " ------- Software radio architecture required for communication systems. Among them, the communication system can reset and reprogram the wireless digital communication system ‘system = 22 two digits to perform different wireless communication standards, services, and applications. In addition, the software-oriented multi-layered architecture of the core-oriented computing unit block of the present invention can improve computing efficiency and provide architectural flexibility. In addition, the present invention provides a hierarchical memory structure, a hierarchical router structure, and a hierarchical bus structure to establish an interconnected network and increase the efficiency of communication channels between computing resources. In addition, the present invention provides a performance feedback and judgment resource management mechanism for adjusting system performance to achieve the goal of optimizing resource utilization. According to the purpose of the present invention, a scalable and extendable multi-level wireless digital communication system is proposed. Each level includes a number of configurable computing units, a number of data flow elements, and a number of control flow elements. These configurable computing units are used to perform wireless digital communication functions, data flow components are used to form paths between these configurable computing units, and these data flow components are capable of storing data. Several control flow elements are used to form a signal ing-exchange network between these computing units. According to the purpose of the present invention, a programmable and reconfigurable-scalable and extensible network is proposed. A method of components in a wireless digital communication system for implementing wireless communication standards, services, and applications. First 'confirm the standard, service or application that will be implemented. Next, compile software that corresponds to a validated standard, service, or application. Then, decide on the use of several hardware resources. Then, reset these hardware resources to execute the confirmed target

TW0724PA (Institute of Electrical Engineering and Technology, Industrial Engineering Institute) · P t d p. 11 200412096 V. Description of Invention (8) Standards, services or applications. Features, advantages, and advantages can be more clearly and easily combined with the accompanying drawings to make the above-mentioned object of the present invention understand in detail, a preferred embodiment is described below as follows. [Embodiment] 0 — The core-oriented computing soap of a wireless digital communication system specially designed by the present invention = a block-based software radio multi-level architecture with a configurable re-prgramming wireless digital communication system Several & pieces to implement Xizhong wireless communication standards, services and applications.切 # ί Invention Description Reprograms and reconfigures these components to perform wireless communications «σ inaccuracy, service, and application technology. Among them, the core-oriented computing unit is based on the SDR multi-level architecture, which can improve computing efficiency and maintain structural flexibility. In order to provide the flexibility of the SDR platform applicable to the base station, the present invention can use a field programmable gate array (fieU pr0grammable, gate 'rr ay, FPGA) to provide sufficient flexibility to the vendors used by vendors Re-configurable hardware. In addition, in order to increase the efficiency of the FPGA, an architecture consistent with the method of the present invention will use an effective arithmetic unit block provided by the FPGA vendor to improve fpga ^ = (Ut 丨 1 11y). The additional glue logic associated with the valid computing unit blocks can establish data paths to provide different standards, applications, and services. The architecture and method of the present invention can provide a one-level memory (1 a y r-m e m 0 r y) structure, a one-level router structure, and a one-level memory.

724PA (Institute of Electrical Engineering and Communication Technology) · _ Page 12 200412096 V. Description of the invention (9) Bus structure to establish an interconnected network, and this interconnected network will comply with the wireless digital communication system and computing resources The characteristics of the region (10caU ty. At the same time, the interconnected I network with hierarchical system 1 can increase the utility of communication channels between computing resources. In addition, the core orientation of the present invention The calculation unit block-based SDR multi-level architecture has a performance feedback-decision resource management mechanism, which is used to adjust the system performance and achieve the optimal goal. Please refer to FIG. 6, which shows a block diagram of a core-oriented computing unit of a wireless digital communication system according to a preferred embodiment of the present invention, which is a basic software-free i-wireless (SDR) multi-level architecture 600. In Figure 6, the RF front-end ϋ02 includes an antenna 604, an RF module 6 06, and a digital frequency up-converter (DUC) m 6 0 8 and a digital frequency. Digital down-converter (DDC) 610. Among them, DUC 6 08 may be an analog-to-digital converter (A / D), and DDC 610 may be a digital-to-analog converter (D / A). In fact, the RF pre-amp waveform processing core 602 | The components included will change with different frequency bands and frequency requirements. Different component combinations will affect the performance of the RF pre-amp waveform processing core 602, and different wireless Digital communication standards, applications and services will also affect the demand and performance of the RF pre-amp waveform processing core 602. SDR multi-layered architecture | Structure 6 0 0 will use pre-designed and pre-tested RF pre-stage waveform processing cores

Η

TW0724PA (Industrial Institute_Telecommunications Institute) .ptd Page 13 200412096 V. Description of Invention (ίο) Heart 6 0 2 to perform the function of RF front-end waveform processing. The present invention performs the function of the fundamental frequency by combining a reconfigurable core and a reprogrammable core. The SDR multi-level architecture 600 includes a one-stage programmable gate array library (FPGA pool) 6 12 and a digital signal processor (DSP) library 614, and the FPGA library 6 12 and DSP library 6 14 both have data. Hardware devices to select and provide different applications and services. Effective hardware devices are selected from FPGA library 612 and DSP library 6 1 4 to provide configurable hardware resources and programmable digital signal processor resources, while reconfigurable cores will operate on FPGAs The reprogrammable core will operate on DSPs. The cores included in the FPGA library 61 2 and the DSP library 6 1 4 in FIG. 6 are sub-operations that can be executed in these devices, and each application program can be broken down into a series of sub-operations. The FPGA library 612 has a reconfigurable core 616, and the reconfigurable core 616 includes processing elements (PE) 618, switch bus (SB) 619, and layer 1 memory (layer 1). 1 memory) 62 0 and switching matrixes 6 2 2. Each PE 6 18 is a basic logical element used to establish the required hardware functions. In the SDR multi-level architecture 60 0, each PE 6 18 is defined as an arithmetic unit block provided by an FPGA vendor and These arithmetic unit blocks from the vendors of FPGA vendors are already the best ^ 2 According to different FPGA architectures, the arithmetic unit blocks include adders, multipliers, correlators or fixed impulse response filters (F j R fi 11 er) Specialized 胄 b ° The different unit block can be used again and can be modified to form different functions, change the parameters and then download again. Heavy

TW0724PA (Institute of Electrical Engineering and Communication Technology) .ptd Page 14 200412096 V. Description of the invention (11) Configuration core 6 1 6 can provide hardware with different special functions and replaces different wireless digital communication standards, applications and AS IC for service. Tier 1 § Self-memory 6 2 0 can provide fast multi-link memory to pass and guide tokens between PEs 618, while Tier 1 memory 62 0 can be connected to the switching matrix 6 2 2 Simultaneous operation to adjust the data transmission and signal flow between PEs. The reconfigurable core 6 1 6 can perform the required hardware functions by interconnecting _ P s 6 1 8 and using a small amount of logic (such as connecting components and different bus architectures) to set the required functions. Among them, the reprogrammable core 624 is a software operation executed on the DSP library 6 12 to perform low-frequency bandwidth functions of digital signal processing, such as automatic frequency control, channel estimation, and compression encoding / decompressor decoding (compressor / decompressor). 5 CODEC) and other functions. By setting the RF pre-level core 6 0 2 and resetting the reconfigurable core 6 1 6 and resetting and reprogramming the core 6 2 4, the present invention will obtain a new baseband function. . Therefore, the present invention will implement a new wireless digital communication standard 'application or service. The interconnected network 630 is a combination of a hierarchical memory structure, a hierarchical router structure, and a hierarchical bus structure for information exchange, setting, and signaling operations. Hierarchical memory structure is used to pass marker tokens between cores, while hierarchical router structure is used to interconnect data and control ports between cores, and hierarchical bus structure is used to transfer between cores. signal of. In order to achieve the purpose of stretching capability, the present invention is to design a global router and a global bus, and the global router and the global bus can operate the interconnection between undefined levels

TW0724PM Gongyuanyuan _ Dentsu Institute) .ptd

200412096 V. Description of the invention (12) and 佗 No. Among them, the hardware processor 6 3 2 (not shown in Figure 6) will control p 7 and control the regional path resources to obtain the path = Connect the network 630 so that The computing unit blocks are based on each other. 6. 0 can communicate with multi-level core-oriented computing unit blocks, such as wood structures and other levels.疋 木 偁 之 具 IJ ί Ϊ 第: V, Jun Qishi is used to perform the wireless digital recitation of Figure 6

Block diagram of Uoo's hardware structure 700. In Figure 7, the hard-use FPGAs and DSPs are configurable and programmable components. In order to use the vehicle, the optimized operation blocks provided by the FPGA manufacturer are used. Better efficiency. Multi-level composition = platform use ^ resource use, and according to the complexity of the implementation of the standard to add or delete hierarchical resources to form a complete non-li ;; two-two structure: the multi-level structure within the extensibility makes ^ Structure 7 0 0 can implement one or more wireless digital communication standards at the same time, and can provide more wireless digital communication standards. The host 704 is used to manage the resources between the layers. In all the layers ^, the performance controller ^ is through the data port ㈠ ... 叩 ^ ⑪)? ^ And control port ’cp 71 °, and monitor the status of the global router 724. Layer 4 (L4) memory 712 is used to store structural data and parameters. The host 704 uses a bridge 714 and a global bus 715 to control the components of the multi-level resource 702. The bridges 7 and 4 can provide an access port. The element for monitoring and controlling multi-level resources 702. The present invention systematically manages memory resources, router resources, and bus resources. TW0724PA (Industrial Institute-Dentsutsugaku) .ptd Page 16 200412096 The five threats from Erming's memory resources have 4 levels to form a hierarchical record. The second level of memory structure includes the structure of Fig. 6 Level 1 (L1) = touch 7. , Stratum 2 (1 ^ 2) memory 718 and 719, stratum 3 (13): 0 and strict stratum 4 (L4) 2 memory 712. Level 1 Memory 6 20 Play

ί f 角色 The role of fast buffer storage, used to provide fast data between PEs = 2 卩 t 2 memory 7 1 8 is associated with the reconfigurable core 6 1 6 and 9 is used for data structure for Marking tokens pass and guide between reconfigurable 1 hearts and 6 hearts. The level 2 memory 7 1 9 is also related to the reprogrammable core 6 1 4. Moreover, each reprogrammable core 624 executes the code of the digital signal processing operation y and provides a data structure for the Information sharing = reprogrammable core between 6 2 4 The level 3 memory 7 2 0 plays multiple levels of the main memory of the source 7 0 2 and is used to store structural data and executable code that can be executed on the hardware manager 6 3 2. Level 4 memory 7 1 2 stores structural data and executable code that can be executed on the host 7 04. The router resource of the hardware structure 700 has a hierarchical router structure ', and the hierarchical router structure includes the area router 722 and the global router 724. The area router 722 is connected to the input / output pins of the core. The I / 0 system of each core is aggregated and divided into two parts, either data port 7 0 or control port 7 1 0. Data port 708 can be designed into a variable length (variaMe-length) structure through the control of control port 710 to modify the length parameters of data port 708 and control port 7 1 0, which can match different core I / 0 different lengths are smoothly connected to each other. The global routers 7 2 4 series provide I / 〇 connections between the hardware resource platform cards (s 1 i c e). The I / O system of each si ice is aggregated and divided into two parts.

200412096 V. Description of the invention (u) Variable-length data bee 708 and variable-length control port 7 1 0. The hardware manager 6 3 2 monitors and controls regional path resources to optimize the path. The reconfigurable core 6 1 6 in FIG. 6 is a high-bandwidth-intensive function performed by different setting elements, especially by different complex programmable logic elements (commpiex). (programmable logic device 'CPLD) FPGAs provided by the vendors' vendors are, for example, Alter Corp. of San Jose, or California 〇 Xilinx, Inc. of San Jose, C a 1 iforni a. Reconfigurable core 6 1 6 series is a functional hardware module used to execute digital logic with timing (critica 1) or high-bandwidth requirements. For the reasons that CPLD vendors know best about their configurable component architecture, CPLD vendors will provide optimized computing unit blocks based on chip area considerations or timing-sense considerations. The arithmetic unit blocks will be considered as basic hardware elements and combined to create parameterized specific hardware functions, such as digital pulse shaping (p u 1 s e s h ap i ng) function, spread / despread function or digital modem. The reconfigurable core is a combination of the reconfigurable core library (1 ibrary) operation unit blocks, which can be used to build the required hardware and improve the performance of the FPGA. The reprogrammable core 624 is a low-bandwidth-intensive function provided by different digital signal processor (Dsp) vendors. DSP vendors such as Texas Instrument, Inc. of Dallas, Texas, Applied Dynamics International, Inc. of Ann Arbor,

TW724PA (Gongyuanyuan_Diantong Institute). Ptd Page 18 200412096 V. Description of Invention (15)

Michigan and Motorola, Inc. of Arlinfton Heights, 1 1 1 i no i s. Reprogrammable core 6 2 4 is a functional software operation program for performing a low-bandwidth DSP function suitable for DSP. The hardware manager 6 3 2 provides an application program interface driver library (d r i v e r s ρ ο ο 1) executable on the microprocessor for data flow planning, resource management, and hardware settings. At the same time, the performance calculator (per for mane e counter) 7 2 6 monitors the real-time status of the radio connection and cooperates with the hardware manager 6 3 2 to perform performance feedback and judge resource management mechanisms, so that the system can be optimized. status. The area bus 7 2 8 is used to connect with the components in the level layer where it is located, and the area bus 728 will transmit data between the components in the area level. The hardware structure 700 includes a multi-level resource 702, and the multi-level resource 702 has a hierarchical memory structure, a hierarchical router structure, and a hierarchical bus structure. Through the use of the hardware architecture 700, different cores from the four parts of the core library can communicate with each other and exchange information through tagging tokens implemented in a hierarchical memory structure. The RF front-end waveform core 6 0 2 is combined to realize the RF front-end waveform processing function, while the rf front-end waveform core 6 2 has a data output of 7 0 8 and control port 7 1 0, which comes from data port 7 0 The signals of 8 and control chun 7 1 0 will be routed to reconfigurable core 6 1 6 and reprogrammable core 6 2 4 via area router 7 2 2 or global router 7 2 4. Data port 708 and control port 710 can handle the control flow and signal flow between the hierarchical router structure and the hierarchical bus structure. This architecture combination can be configured with a hardware core and a programmable software core.

TW0724PA (Industrial Institute_Telecommunications Institute) .ptd Page 19 200412096 V. Description of Invention (16) The architecture simultaneously implements one or more existing wireless digital communication standards and provides the implementation of future wireless digital communication standards. The core can perform computation-intensive processing functions, which can be executed by the cooperation between FPGA program code or DSP program code and FPGA and DSP. According to which standard or service will be implemented, the appropriate core is selected from different core libraries to meet a specific standard or service specification. The configuration data of the configurable core 6 1 6 and the executable code executed on the programmable core 6 2 4 are stored in the L3 memory 720. After reconfiguring the individual configurable cores 6 1 6 and the programmable cores 6 2 4, the information exchange between each other will be combined through the interconnection of the hardware architecture 7 0 0 and the guidance of the tokens. Together 0 The interconnected network 6 of FIG. 6 includes a hierarchical memory structure, a hierarchical router structure, and a hierarchical bus structure, and the interconnected network 6 3 0 is used to connect the RF front-end waveform core 6 0 2 , Reconfigurable core 6 1 6, reprogrammable core 6 2 4 and hardware manager 6 3 2. The core system can be selected from different core libraries, and each core system can be controlled by the corresponding software operation. By selecting the appropriate core from the core library, the functions of the hardware architecture will be easily converted from a wireless digital communication system to another system. Please refer to FIG. 8, which shows a block diagram of a private sequence of 8000 performed in the hardware architecture 7000 of FIG. 7. In Figure 8, the dynamic library 802 includes wireless, functional signal processing modules, real-time control modules, and hardware interface modules. Dynamic library 802 has real-time connection function for real-time operation. This technology is used for dynamic connection information in the operating system. The application program 804 can be compiled into an executable slot by a compiler,

200412096 V. Description of Invention (Π) Case 806, the application program 804 can be a wideband code-division multiple access (WCDMA) and a wireless area network. The download function of the dynamic library 802 enables the reconfigurable manager 810 to download a new library from a network or a library to a hardware unit from a storage unit. The required resource parameters 81 2 generated by the executable file 8 0 6 will be transmitted to the reconfigurable manager 8 1 0 'for generating application-specific interface configuration files (prof i les) 814. At the same time, the executable file 806 located in real-time operation time includes connection information of hardware-related programs of a specific air-interface application, and the hardware-related programs are, for example, DSP code and hardware description language ( hardware description language (HDL) code. Moreover, the executable file 806 is generated by the compiled application program and the wireless communication function function from the dynamic program library 802. AP I profile 8 1 4 can be converted to operating system (OS) 8 1 6 or hardware manager 6 3 2 in Figure 7. The hardware manager 6 3 2 performs mapping between software architecture and hardware architecture (mappi ng) according to the current state of the radio environment and resource utility. The hardware manager 6 32 contains a radio resource use control driver 8 2 2, an environment discovery driver 8 2 4, a hardware configuration driver 8 2 6 and a download driver 8 2 8. The radio resource usage control driver 8 2 2 is used to record and maintain the utility table in the hardware resource, and the environmental discovery driver 8 2 4 is used to monitor and record the current radio environment. According to the status of the radio resource usage control driver 8 2 2 through the hardware abstraction layer (HAL) 83 0 mapping provided by the hardware resource utility information, then HAL API 83 2 to HAL driver 83 4 Of

TW724PA (Industrial Institute_Telecommunications Institute) .ptd Page 21 200412096 V. Description of Invention (18) A one-to-one path system can be reserved in advance. H A L 830 is a layer of a computer program that allows an operating system to interact with a hardware device. The hardware device is on a common or abstract layer, rather than on the detailed hardware layer. The hardware configuration driver 82 6 is used for effective mapping in the API configuration file 81 4 and the HAL driver 8 3 4, and the download driver 8 2 8 is used to download the executable file 8 0 6 in the HAL driver 8 3 4 Save the program in the selected support driver. After the hardware configuration driver 8 2 6 and the download driver execute the above procedures, different kinds of HAL drivers 834 will be downloaded to specific hardware devices in a multi-level architecture 7 0 0, so that the present invention can Simultaneously implement one or more wireless digital communication standards, and provide the implementation of future wireless digital communication standards. Among them, the above-mentioned different types of H A L drivers 8 3 4 can be A D C drivers, D A C drivers, and data driver, and the specific hardware devices can be amplifiers 836, FPGA 838, and DSP 840. The mapping between functions and cores will change according to the requirements of different wireless digital communication §fl applications. The judgment criterion of the standard-driven architecture disclosed in the present invention lies in several parameters. These parameters include data throughput, latency, latency, number of I / O pins, area, Memory requirements: dual energy and power consumption. According to the radio environment and resource utility table, 632 can coordinate whether effective resources can better fit into these parameters of m to record the services required in the state. Therefore \ / ^ # is sufficient to implement the reconfigurable and reprogrammable specific hardware resources =

200412096 V. Description of the invention (19) Sequence 8 0 0 was used again. After selecting the appropriate core according to the radio environment and resource utility table at that time, the relative data structure that can be exchanged for tokens will be determined by a new data flow and a new control flow. Please refer to FIG. 9 ′, which shows a block diagram of the core-oriented computing unit block of FIG. 6 based on a hierarchical structure of 960 with a hierarchical structure of 6 0 0 and a hierarchical structure of 0 0 0. In Figure 9, this core may be the RF pre-stage waveform processing core 6 0 2, the reconfigurable core 6 1 6 or the reprogrammable core 6 2 4. Area router 7 2 2 and L 2 memory 71 8 (or L2 memory 719) are formed by data port 7 0 8 and control port 710

A network of data flows between these cores, regional buses 7 2 8 via data ports

7 0 8 and control port 7 1 0 form the signal flow between these cores. That is, each layer has a layered resource structure according to the new wireless digital communication standard or service, which is used to be reset and reprogrammed to meet a new demand. The hierarchical resource structure of each hierarchy mainly includes a hierarchical memory structure. The hierarchical memory structure includes L1 memory 6 2 0, L2 memory 718 and 71 9, L 3 memory 7 2 0, and hierarchical router structure. Area router 7 2 2 and area bus 7 2 9 of the hierarchical bus. Please refer to FIG. 6 again. The L 1 memory 6 2 0 belongs to the reconfigurable core 6 1 2 and establishes a fast communication channel between the processing elements (PE) 6 1 8. The data flow part gathered by the reconfigurable core 6 1 6 should require L2 memory 7 1 8 to form a communication channel between the reconfigurable core 6 1 6. Similarly, the data stream part gathered by the reprogrammable core 6 2 4 also needs L2 memory 7 1 9 to form a communication channel between the reprogrammable core 6 2 4. L 3 memory 7 2 0 is the main memory of the hierarchy and stores configuration data and executable code to provide the hardware manager

TW0724PA (Industrial and Industrial Institute_ Dentsu Institute) · Ptd

200412096 V. Shouting instructions (20) 6 3 2 Perform software operations and management of greed. Please refer to FIG. 10, which shows a three-dimensional block diagram of the hierarchy system 90 of FIG. In Figure 10, this architecture divides resources into three parts, where t is the arithmetic unit, data flow, and control flow. The arithmetic unit includes an RF pre-stage waveform processing core 6 0 2, a reconfigurable core 6 1 6 and a reprogrammable core 6 2 4. These cores usually perform the tasks of wireless digital communication functions such as waveform processing and digital signal processing. The requested path and storage will define the data flow to form the data exchange network between the computing units, and the data flow includes hierarchical memory / structure 'and hierarchical router structure. The required path and storage will define the J data flow to form a signal exchange network (signa 1 ing-e X change network) between the computing units, and the control flow also includes a hierarchical memory structure and a hierarchical bus structure. The core shown in Figure 10 can be an RF pre-stage waveform processing core 6 0 2, a reconfigurable core 6 1 6 or a reprogrammable core 6 2 4. These cores are aggregated to create functional blocks to simultaneously implement one or several wireless digital communication standards at the time and provide future wireless digital communication standards. When an event of a new standard, application or service occurs, the present invention will select a corresponding parameter and resource to meet the demand. Parameters include data flow, delay time, number of I / 〇 pins, area, memory requirements, performance requirements, and power consumption, and resources include hardware resources and software resources. The hardware resources provided by this architecture include RF pre-stage waveform processing core 6 0 2. Reconfigurable core 6 1 6. Reprogrammable core 6 2 4. Hierarchical memory structure, hierarchical router structure and hierarchy Bus structure to provide rigid

TW0724PA (Industrial and Electrical Engineering) .ptd Page 24 200412096

V. Description of the invention (21) The body needs and forms an event-oriented platform. The executable software resources of the hardware manager 6 3 2 are used to handle the observable and controllable functions of wireless digital communication. The reconfigurable core 6 1 6 and the reprogrammable core 6 2 4 are designed as a parameter-based hardware structure. This parameter is downloaded to the FPGA and DSP based on the optimization of a specific algorithm. In order to distinguish the data flow and the control flow to improve the operating speed between the cores, the present invention will provide an out-of-band technology. This architecture uses FSB technology, and cooperates with hierarchical router structure, hierarchical bus structure, data port 708 of different lengths and control port 7 10 of different lengths to coordinate different speeds between data flow and control flow . The performance feedback and judgement resources mechanism monitors and analyzes some parameters through the performance calculator 7 2 6 to determine which resource's utility should be changed to achieve the goal of optimization. Please refer to Figure 11 for a flow chart of the execution procedure of the dynamic hardware configuration 1 1 0 0. In Fig. 11, in the step of performance estimation (1 102), the present invention monitors the performance through the performance calculator 7 2 6. The result estimated by the performance calculator 726 will be compiled into a status report (104), and this status report (104) will be stored in the L3 memory 720. Radio management information base (RMIB) 1106 is a database of radio connection related performance parameters, and the performance parameters are such as signal-to-noise radio (SNR) and channel impulse response, CIR) and other parameters. The estimated results recorded in the status report (11 04) will then be compared with the relative parameters recorded in RM I B 1 10 6. If the result of the comparison is greater than expected

TW0724PA (Institute of Industry and Technology—Telecommunications Institute) .ptd Page 25 200412096 V. Description of the invention (22), the invention will cause an interruption condition to notify the hardware manager otherwise, return to the step of performance estimation (11 0 2) Value (1108) 632 (1 1 1 0) steps. Then, the hardware manager 6 3 2 will notify the SDR-general manager (111 2) according to the interruption caused, and the SDR-general manager (111 2) will read the information from the status report (111 4). Detailed status information. Next, analyze this detailed status information and select a suitable algorithm to generate a new configuration structure. The SDR-general manager (111 2) instructs the reconfigurable manager 8 1 0 to change the current configuration structure (111 6). The reconfigurable manager 810 will then generate a modified algorithm file (111 8). The reconfigurable manager 8 1 0 will then inform the hardware manager 6 3 2 to process the new configuration structure (1120). Radio resource utilization information base (RRUIB) 112 2 is a database recorded in the utility table of all hardware resources, and the hardware manager 6 3 2 stores all hardware resources and uses radio resources. The control driver 8 2 2 will save these hardware resource utility tables. Then, when the hardware manager 6 3 2 receives the modified algorithm file, the hardware manager 6 3 2 will read the saved resource utility table of RRU IB 1 1 2 2 and check if there are enough hardware resources available. Run this modified algorithm file (11 2 4). If the available resources cannot process the modified algorithm file, the hardware manager 6 3 2 will send a status report to notify the SDR-general manager (1 11 2), and explain that the currently saved hardware resources cannot support the Demand algorithms to improve performance. If the available hardware resources managed by the hardware manager 6 3 2 can execute the modified algorithm file, the hardware manager 6 3 2 will start core synthesis

Η T1V0724PA (Industrial and Technical Institute_Electric Communication Institute) .ptd page 26 200412096 V. Description of the invention (23) Supporting hardware (sy n t h e s i s) operation (1 i 2 6). The core synthesis is a real-time program that selects hardware computing unit blocks and software operations that perform better and executes the required algorithms. There are currently 2 libraries that provide the required optimized hardware resource computing unit blocks and software operations. One is a computing unit block-based library 1128 to support different types of optimized hardware computing unit blocks provided by different configurable devices. The unit block-based library 112 8 can come from CPLD. Vendors who have scrapped business, such as ALTERA, Xilinx, and Lucent. Another library is a subroutine based library 1130. Use the ^ base to select the appropriate optimization operation. The meta box (1128) and Yuzi There are many different types of optimization routines provided by different programmable devices, and the subroutine library 11 30 can come from DSP vendors such as TI, Motorola, and ADI. The library is based on the arithmetic unit block After a software operation (U30) is selected from the basic library, the present invention becomes a new algorithm. The hardware configuration driver 8 $ of the hardware manager 6 3 2 is mapped with the supported driver (U32). Hardware manager 63 ^ series Download driver 8 2 8 is used to reconfigure and reprogram the relative < core and programmable core (11 3 4). The emergence of anger cases, the inspection of the use of radio resources, the resettable and reproducible core of the synthesis and standard ^ Xinbei 2 2 "People" style. Via Yixianxue, using the control driver 8 2 2. Hardware configuration to drive down ~ After the joint operation of the type 82 8, the execution process of the hardware 826 and download driver complex dynamic hardware configuration 1100 is closed. Lost-loop) program, which includes performance estimation, new generation, radio resources # 田 + k Μ ^ ^ ^

200412096 V. Description of the invention (24) In addition, the present invention achieves performance feedback and judges the resource management mechanism by executing a closed loop procedure of dynamic hardware configuration 1 100, and finally downloads the executable file to the area where it is available Reset the component. When the present invention uses the performance feedback and judgment resource management mechanism, the current status of the radio connection can be immediately transmitted. Parameters related to radio connection performance such as SNR and CIR will be returned via the performance calculator 7 2 6 to determine which resource's utility should be dynamically changed to meet the dynamic characteristics of the wireless channel's wireless channel and achieve the best Goal of transformation. Since the architecture of the present invention uses pre-set and optimized operation unit blocks provided by different configurable component manufacturers, this architecture uses the operation unit blocks as the basic structure. Please refer to FIG. 12, which shows a block diagram of the execution program of the configurable design based on the operation unit block of the present invention. In Figure 12, 'standards or services can be divided into p squares, and these P squares are defined as AP I 1 1 2 0 2, ... AP I p 1 2 08, which are used to individually describe the relative basic functions. . Different design constraints such as data flow, delay time, complexity, and power consumption will use different algorithms to implement the same functional blocks. In other words, an API can contain many versions that are executed based on different methods of disparity. For example, candidates for performing the same functional block of API 1 1 2 2 are selected between algorithm 1 · 1 1 2 0 4 and algorithm n 1 2 0 6. On the other hand, V ^ to perform the same functional block candidate of AP I P 1 2 0 8 is selected between the algorithm p 1 1 2 1 0 and the algorithm p · n 1 2 1 2. ， Open ’· This architecture is based on the vendor defined macro library 1214 as the target library.

200412096 V. Description of the invention (25) Synthesis design. The operator unit library defined by the operator manufacturer and the vendor library are named as the vendor manufacturer " 瞀 M library 1216, the vendor manufacturer 2 computing unit block program, and the fan manufacturer 1218, ^, The unit block library 1220, such as tLTERA, Xilinx, and Lucent, can be configured in different ways. The way the unit block library 1214 can be placed is == Placed and routed (P & R) ( 1 224, AND: Many versions of the algorithm 1.1 · 1 1 204 can be produced). . == 8 '八 1 ^ £ 88 The eighth version of the algorithm 11 is one of the algorithms 1; 1 1204 which can be executed # 早 ^ ， 中The hardware manager 6 3 2 may have chosen a XiHnx version. Or a Lucent version of the algorithm. At the same time, other systems that belong to Αρι and industrial f 1 can perform the same functions as the algorithm hl 1204, but they have different design restrictions and are applicable to different radio environments. The calculation ^ ^ = 1 2 0 6 can also be combined (1 2 2 2) and p & R (1 224) to generate a ^ vendor manufacturer version to perform actions and implement algorithms in different states 丨 from different vendor manufacturers The supported arithmetic unit block library is beautiful_ ^ 1 1 2 0 2 The compiled results of different algorithms will be gathered: ^ Form API 1 related arithmetic unit block cell (ceU) library i2, 乂 f outside 'APi f API 3,... And API P 1 2 0 8 have their own relative operation unit block cell libraries, just as Ap 丨 p 丨 208 has API P related operation unit block cell libraries ι 2 32. By aggregating all ^ 丨 related arithmetic unit cube cells from 1 1 2 02 to API p 12 08

Ｍ Page 29 200412096 V. Description of the invention (26) After the library, the library 11 2 8 based on the arithmetic unit block can be generated to execute the basic functional block, and different combinations of these blocks can execute the selected one. Standards, services and applications.

Please refer to FIG. 13, which shows a block diagram of the core-oriented computing unit block of the wireless digital communication system of the present invention, which is based on the S D R multi-level architecture 1 300. In Fig. 13, the SDR multi-level architecture 130 is a structure similar to a chassis-1 ike. The multi-level resources 1 30 2 are connected to a back-plane 1 304, and the back-plane 1 304 includes a global bus 7 15 and a global router 724. Each layer of the multi-level resource 1 302 is a ^ this component, which is used to operate on this case and can provide wireless plug-and-pi ay functions. One way to obtain wireless plug-and-play is to provide an event-initiated (e v e n t -1 r g g e r e d) structure, while the other method is hard-insertion and resource detection. Since this event-triggered structure can be provided in this architecture, when a new event of a standard, application, or service occurs, the environment found by the hardware manager 6 3 2 ^ driver 824 is raised, and the relative parameters and resources Will be cut ^ · Guchi required performance. ,

The effective resources determined by this procedure include the static hardware sequence of 80 0 and a flexible operation unit block as the execution of the infrastructure% ^ sequence 1 ^ 2 0 0, and 1 poor source is caused by events provided by this architecture A part of the structure. The other part is used to provide a performance feedback and judge resource management. Ϊ́ίίΐίϊίΓ Configuration 1100-execution procedures to fine-tune the service capabilities to provide additional user services, FireWire ϊΐϋ

More · 4 · sound · 200412096

5. Description of the invention (27) The ability to detect is to help stretch. The new wireless digital communication standard, application or service requested by the user will be sent by limited or wireless access, and manually switched to a service request from a non-volatile memory on the slice. . The event detected by the $ event triggering structure will cause the hardware manager 632 to find available hardware resources on this chassis and prepare to download a new ^ executing operation 'to reconfigure, reprogram, and create a The requested platform is new. If the available hardware resources are unable to implement the new wireless digital communication standards, applications or services, the lack of hardware and the number of s i c e will be verified, so the new hardware resources can be obtained and increased. Performance calculator 7 2 6 Monitors and calculates the performance of the radio connection periodically to report the f-state of the helmet soul mine. It is used to rearrange resources after assessing the performance of the operation. In addition, after the new functions or different rendering methods are selected, the hardware manager 6 3 2 will trigger the hardware configuration driver 8 2 6 and download the driver 8 2 8 to reconfigure and reprogram. This target hardware resource. The cooperation between event-oriented configuration capabilities and the interconnection of the hierarchical system will improve the demand for different speeds and increase the data flow of the system. After feed forward (fee (if orward)) through the group's forgiveness and program target core, this architecture will provide a performance feedback and judgment resource management mechanism to integrate and sadly maintain the full computing power of the system, and Improve the effectiveness of resources. In addition to the ability to organize and combine the same resources, such as to organize the core and interconnected networks that can create new wireless digital communication standards, applications and services The ability of multiple standards. That is, two or more standards can coexist and work together.

200412096 V. Description of Invention (28) Industry. By using the remote antenna port (RAP) 1306, the new architecture can be used as a centra 1-control 1 ed base-station set center to replace the base of the base station. Frequency signal processing function. In other words, the original position of the base station is used to convert the waveform from the antenna and RF module. Other operations of signal processing will be moved to the central control base station setting center to manage hardware and software resources. m When the {^ previous waveform core at the original location where the base station is located provides an RF preamp function, the complex signal processing functions will be moved to the central control base station setting center and executed in different levels to achieve Implement multiple standards, applications and services for different purposes. The remote control antenna can replace the original base station that cannot handle the baseband function to handle analog waveform processing. Therefore, the weight, size and complexity of the original base station will shrink. Digital signals from different places of the remote control antenna can be received through a variable-length remote control antenna port, and the digital signals will be gathered at the central control base = setting center for common processing. The software radio of the wireless digital communication system disclosed in the above-mentioned embodiments of the present invention has the following advantages: 1. The wireless digital communication system can reset and reprogram the components of the wireless digital communication system 'to perform wireless communication standards, services, and applications.

2. The core-oriented computing unit block of the present invention is based on the "sdr multi-level architecture, which can improve the contradiction between efficiency and flexibility. 3. The present invention provides a hierarchical memory structure, a device structure, and a hierarchical bus以 to establish an interconnected network and increase

Guang 4 to 200412096 V. Description of the Invention (29) Add the utility of the communication channel between computing resources. 4. The present invention has a performance feedback and judgment resource management mechanism to adjust the system performance and achieve the goal of optimization. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. Φ

TW0724PA (Industrial Institute_Electric Communication Institute) .ptd Page 33 200412096 Brief Description of Drawings Figure 1 shows a block diagram of a general wireless digital communication system used to implement a single communication standard. Figure 2 shows a block diagram of a general wireless digital communication system for implementing multiple communication standards. Figure 3 shows a block diagram of the control architecture of a general multi-standard communication device. Figure 4 shows the relative relationship between efficiency and flexibility presented by different hardware. Figure 5 shows a block diagram of a wireless digital communication device that implements multiple communication standards. FIG. 6 shows a block diagram of a multi-layered SDR-based architecture of a core-oriented computing unit block of a wireless digital communication system according to a preferred embodiment of the present invention. Figure 7 shows a block diagram of the hardware structure of a multi-layered SDR-based architecture based on the core-oriented computing unit block of the wireless digital communication system shown in Figure 6. Fig. 8 shows a block diagram of an execution procedure performed in the hardware architecture of Fig. 7. Figure 9 is a block diagram of the hierarchical architecture of the core-oriented computing unit block of Figure 6 based on the SDR multi-level architecture. Figure 10 shows a three-dimensional block diagram of the hierarchical architecture of Figure 9. Figure 11 shows a flowchart of the execution procedure of dynamic hardware configuration. Figure 12 shows a block diagram of the execution program of the reconfigurable design based on the block of the arithmetic unit of the present invention.

TTO724PA (Institute of Electrical Engineering and Communication Technology) .ptd Page 34 200412096 Brief description of the drawings Figures 13 and 3 show the hardware structure of the core-oriented computing unit block of the wireless digital communication system of the present invention based on the SDR multi-level architecture Block Diagram 0 Schematic Symbol 100 102 104 106 108 110 112 114 116 118 120 122 124 202 300 500 502 504 506 Description > 2 0 0: Wireless Digital Communication System_ .6 0 4: Antenna Radio Frequency (RF) Subsystem Intermediate frequency (I / F) subsystem Analog-to-digital converter (A / D) subsystem Dedicated logic element 508: Bus programmable logic element 840: Digital signal processor (DSP) Microprocessor software unit 816 · • Operating system (OS) application-specific logic component library control architecture wireless digital communication device programmable digital signal processor programmable microprocessor heterogeneous reconfigurable multi-processing logic circuit

TW0724PA (Industrial Engineering Institute_Diantong Institute) .ptd Page 35 200412096 Simple illustration of the diagram 51 〇: Heterogeneous signal processing software core 5 1 2: Programmable digital signal processing core 5 1 4 ·· Programmable microprocessor core 5 1 6: Executable code 518, 610 ... Digital frequency shift down converter (DDC) 519, 6 0 8: Digital frequency shift up converter (DUC) 6 0 0, 1 3 0 0: Software radio Multi-tiered architecture 6 0 2 ······························-···········-·································· 6 · Reconfigurable core 618 ·· Processing element (PE) 619: Switch bus (SB) 6 2 0 · Level 1 memory 6 2 2: Switch matrix 6 2 4 ·· Reprogrammable core 6 3 0 : Interconnection network 6 3 2: Hardware manager 7 0 0: Hardware structure 7 02, 1 3 0 2: Multi-level resources

704: Host 7 0 6: Performance controller 708: Data port TTO724PA (Institute of Industry and Technology—Telecom) .ptd Page 36 200412096 Simple description of the diagram 710 · 712 714 715 718 720 722 724 726 729 800 802 804 806 808 810 812 814 822 822 824 826 828 830 832 Control port level 4 memory bridge global bus 7 1 9: level 2 memory level 3 memory area router global router performance calculator area bus 1 2 0 0: run program dynamics Library application executable file compiler reconfigurable manager resource parameters application programming interface (API) profile radio resource usage control driver environment discovery driver hardware configuration driver download driver hardware abstraction layer ) HAL Application Programming Interface

TW0724PA (Industrial Institute_Telecommunications Institute). Ptd Page 37 200412096 Simple illustration 834: 8 36: 838: 9 0 0: 1100 1106 1122 1128 1130 1202 1204 1206 1208 1210 1212 1214 1216 1218 1220 1230 1232 1304 1306 HA Programmable amplifier field-type programmable gate array hierarchy architecture dynamic hardware configuration radio management information library (rruib) operation unit block-based library subroutine-based library API 1

Algorithm 1. 1 Algorithm 1. N API P Algorithm P. 1 Algorithm P. N Vendor Vendor 1 Operation Unit Block Library Vendor Vendor 2 Operation Unit Block Library Vendor M Operation Unit Block Library AP I 1 Related Operation unit cube cell library AP IP Related operation unit cube cell library back panel remote antenna port

TW0724PA (工 硏 院 _ 电 通 所) .ptd $ ·· Η44 ： · Page 38

Claims (1)

200412096 6. Scope of patent application 1. An upgradeable and extensible wireless digital communication system, including: a plurality of hardware resource platform cards (s 1 ice), each of the hardware resource platform cards includes: a plurality of groupable A state-of-the-art computing unit for performing operations of a wireless digital communication function; a plurality of data stream components for forming a plurality of paths between the configurable computing units, and the data stream components being capable of storing data; And a plurality of control flow elements for forming a signal exchange network between the computing units. 2. The wireless digital communication system described in item 1 of the scope of patent application, wherein at least one hardware resource platform card of the hardware resource platform cards can communicate with another hardware resource platform card. 3. The wireless digital communication system described in item 1 of the scope of patent application, wherein the configurable computing units include a radio frequency pre-processing waveform core group, a reconfigurable core group and a reprogrammable Core group. 4. The wireless digital communication system described in item 1 of the scope of patent application, wherein the data stream components include a hierarchical memory structure and a hierarchical router structure. 5. The wireless digital communication system described in item 1 of the scope of patent application, wherein the control flow elements include a hierarchical memory structure and a hierarchical bus structure. 6. — Programmable and configurable-upgradeable and extensible 200412096 VI. Method for applying patents to components in a line digital communication system to execute multiple wireless communication standards, services and applications, the method includes: confirming the standards, services or applications to be performed; compiling a phase Software corresponding to the standard, the service, or the application that has been confirmed; determining the use of multiple hardware resources; and resetting the hardware resources to execute the standard, the service, or the application that has been confirmed. # TW0724PA (工 硏 院 _ 电 通 所) .ptd Page 40