200412026 玖、發明說明： 【發明所屬之技術領域】 本案係2002年4月8曰申請之美國專利申請案號第 10/1 1 8,733以及於2002年5月2曰申請之美國專利申請案號 第10/137,988的部分連續申請案，其主張2〇〇1年9月5日 申請之美國專利申請案號第09/947,643(現為美國專利案號 第6,322,595)之優先權，上述皆合併於此以供參考。 本發明一般係關於積體電路設計之區域，特別是與用 於高速信號之積體電路的改良設計及其方法有關。 【先前技術】 未來通訊網路的需求都會因不同的通訊協定而增加頻 寬以及其彈性。光纖網路由於其高速及高承載能力，在數據 傳輸上已廣泛的運用。波長劃分多工器（Wavelength division multiplexing，WDM)係為一種將不同來源的資料與不同光波 長上同時間所載送的每個信號一起放在光纖上的技術。使用 該WDM系統，高於80以上之不同波長或資料通道可以多工 方式成為傳輸於一單一光纖上的光資料流。現已預期通過光 纖上經調變之單模雷射光束其内含之光學資料傳輸率應會 遠超過 l〇〇〇Gbit/sece 目前，實際可行之光纖通訊系統的頻寬仍受限於光與 電子網域及相關電子硬體間的信號轉換。使用於現行光纖通 訊系統（例如同步光纖網路）的主要元件為光學傳接器，其係 200412026 結合傳送/接收於一單_ τ 一封装内。在沿一光纖網路之一來源、 一目的或一主要介面沾仓 的每一介面中都可發現光學傳接器。除 了光纖通訊應用外，意从^ 具他的應用或系統亦可使用傳接器來接 收或傳送高速資料，你丨1 ^ 例如無線通訊元件。 現行用於高速衿^ 及15唬之傳接器係採用鍺化矽（SiGe)、砷化 蘇（GaAs)鱗化鋼（Inp)等製程，然其以現行技術而言仍屬昂 貴’較大規模傳接器的製程費用仍不符合經濟效益。因此， 便有種α计需求係能以較經濟、較低成本的方式製造該等傳 接器 【發明内容】 此*章節以及本發明摘要係為描述本發明之某些態樣， 並簡紐地介紹一或多個較佳實施例。此處的簡化或省略係為 避免模糊了本章節及摘要的特點。然該等簡化或省略並非用 以限制本發明之範圍。 本發明係關於可用於許多電路及電路系統中之差動放 大器（differential amplifiers)的整合設計。現已知於個別元件 上（例如電晶體及電阻器）的寄生效應會在該等信號頻率超過 某一範圍時將假影（artifacts)引入該等信號中。本發明之一目 的係有系統地調整該等元件，利用該寄生效應來減少該等信 说内之該些假影。 依據本發明之一態樣，一定義為電性等同幾何 (Electrically Equivalent Geometry,或 EEG)的參數係定義為 200412026 一寬度及長度的函數，其係限定一控制多少電流能通過之一 部份電晶體。例如由佈局透視圖中可知，一 EEG係與一 MOSFET電晶體的閘極區域或一雙極式電晶體的發射區域有 關。適當調整不同放大器或電路中各電晶體的EEG可降低致 使訊號出現假影的該些寄生效應，同時也會形成原有的諧振 濾波功能以減少輸出訊號中的諧波分量。 為更能降低該些寄生效應在信號内所形成的假影或形 成適當之諧振濾、波功能，其他個別元件（如電阻器）可作系統 性的调整。每一該等元件係與一稱為電性等同元件參數 (EECP)之參數有關，其亦為定義一半導體區域之寬及長的函 數以用於製造該元件。適當調整該等元件的EECP與該等電 晶體之EEG，不但能夠容納更高的信號速度，也能處理更高 量的輸出信號。 為進一步提昇一差動放大器或電路的能力以容納更高 的信號速度，係採用電感性元件（例如電感器及變壓器）並作 系統性的調整。來自該些電感性元件的電感會因此降低該些 會導致信號產生假影的寄生效應，使差動放大器或電路具有 容納更高信號速度的能力。 本發明尚有許多優點及特徵，其中之一係以不同於習 知方法的設計方式，使一差動放大器或電路能容納該些未能 容納於該差動放大器或電路中更高之信號速度。本質上，本 發明係可執行於高速系統，例如以較低成本之半導體製程（互 補式金屬氧化半導體，0·18微米製程）處理較大規模的光纖 200412026 或無線通訊。 本發明之其他目的、特徵以及優點將配合附加圖示並 藉下文所將詳述之較佳實施例而更得以彰顯。 【實施方式】 本發明係關於差動放大器之整合性設計，其可用於許 多電子電路及系統中。週知個別元件上（如電晶體及電阻器） 的寄生效應會在該等訊號的頻率超過某一程度範圍時將假 影引入訊號中。本發明之-目的係利用該寄生效應有系統地 調整該等元件，來幫助減少該等訊號内之該些假影。 本發明之詳細說明概以程序、步驟、邏輯區塊、製程 或其他符號表現所呈現，可直接地或間接地表示搞接於光纖 網路之信號處理裝置的運作方式。這些說明與表現方式即為 該專熟諸本項技藝之人小ή&，、，旦, « +只仪β <人士為以最有效地將彼等工作傳達予 其他業界人士本質内容所採用的 I休用的途徑。在此，「一具體實施 例」或一「具體實施例|避士田S_ %明疋扣關聯於具體實施例所描述 之某特定性能、結構或特徵，可祜冬 1 ^ 』破3納於至少一本發明具體 實施例之内。在本規格書裡夂虛 宵粗谷處出現的「在一具體實施例中」 詞彙並不必然地皆指稱於夫日η从曰Μ也 、相同的具體實施例，而個別或替代 性具體實施例亦非互相斥峪认甘Μ Μ θ 仰吓除於其他的具體實施例。 現在參看該些圖示， 其中冋樣數字於所有圖示中均表 示同樣元件。第1Α圖係褚日日亦田认 , 于况明可用於一光纖網路之一例示性 之傳接器100。該傳接器 10 0包括兩個功能區塊、一接收器 102以及一傳送器1〇4。_ 光-電轉換器1 〇 3 (例如一光電二極 200412026 體）係將該等光學信號轉換成電子信號而由該接收器102接 收。該電子信號由一轉換電阻放大器（TIA) 1〇6放大，並進一 步由一限輻放大器108放大為一適當之信號範圍。於該限輻 放大器108後係為一時脈資料回復（CDR)電路1 1〇,其包括一 鎖相迴路（PLL)，此處並未圖示出《由該限輻放大器經 放大之信號因而鎖住，且呈電子信號形式之資料以及其中之 時脈訊息會被回復。一 DeMUX 11 2係用於解多工該等資料 以維持多重通道，例如 OC-3(155Mbits/s)、〇C-12(622Mbits/S) 以及OC-48(24 8 8Mbits/s的速度）。於另一端，該傳送器ι〇4 包括一 MUX 118可多工處理來自數個通道之信號，以得一 信號可在到達一驅動器114前先通過其他電路116，以提供 該些信號予一光_電轉換器1〇3(例如一雷射產生器）。 第1B圖係表示一可用於無線通訊元件之例示性傳接 器130。該傳接器130亦可包括兩個功能性區塊、一接收器 132以及一傳送器134。該接收器132接收來自一天線13 3 之電子信號，且該電子信號接著於一低雜訊放大器丨36中放 大至某一強度，而該經放大之信號接著於一混頻器138中與 一來自震盪器135之震盪信號混合，接著輪出一或多個適合 進行隨後類比-數位處理之信號。於一應用中，該混頻器i 3 8 可發揮一降頻器的功用來接收源自該震盪器135之49GHz 仏號。於另外一端，該傳送器134接收資料並於一調幅器"ο 中調變該等資料。該經調變之信號係升頻於一變頻器142中 以符合來自該震盪器135之震盪信號，並在到達天線133發 送前先進一步於一功率放大器144中放大。 200412026 此處未進一步將亦使用傳接器之其他應用或系統列 出，於第1A或1B圖中該傳接器處理該等通過信號的速度在 光纖網路或無線通訊元件中影響至深。為確保傳接器能處理 高速信號（例如40GHz或lOOMbits/second的速度），在該傳 接器中每一功能性區塊必須能處理該信號速度而不致將假 影引至該些信號中。 許多功能性或建構區塊現在都使用差分輸入以提昇表 現。通常，在通過一類比-數位轉換前，都需經振幅、阻抗匹 配、濾波以及位準偏移等電路元件，並使用一或多個差動放 大器或電路。應暸解的是，完全的差動電路不僅能滿足這些 條件，也能有效簡化設計任務。此外，能夠與相同基材上同 樣7L件特性相匹配的設計會大量使用對稱性來作為濾波機 制。該差動放大電路配置在此態樣中尤其重要。 現參照第2圖，其表示一包括三個差動放大器202、2〇4 及206(該等差動放大器206的細部並未示出）之差動電路 200，而該等差動放大器其係以常見於功能性區塊中建立— 傳接器或其他電路的方式作耦接。應可預期的是，一電流源 208提供所欲之電流I，且該等熟習此項技術者應可瞭解二分 之一電流I即可驅動各放大器2〇2或206，因此只有1/2之 電流I通過各電晶體T3及T4。就該放大器2〇2而言，其係 由1/2之電流I所驅動（由該放大器2〇4)且因此將有ι/4之電 流I通過各電晶體T1及T2。於習知技術之設計中，該等電 晶體T1或T2及T3或T4 一般係按電流通過比例設計之。 200412026 然而’當通過該電路200之信號速度增加，寄生效應 會開始扮演扭曲信號的角色，此時若該電路200仍以習知使 用的方法設計並執行，將會因而限制該電路200可處理或容 納的速度。 值得注意的是除了習知方法外，本發明係揭露利用及 4整該寄生效應，並建立諧振效應的技術以提供濾波功能來 與該等因南速信號形成之寄生效應所引入的假影「搏鬥」。 依據本發明之一態樣，各種電晶體係分別對應寄生電容而調 整為相對增加/降低，以使固有濾波的該等寄生效應及諧振效 應可有效且順利的使用。依據本發明之另一態樣，係採用若 干電感器以進一步降低該等引發假影之寄生效應，並形成更 多適當之諧振效應以進一步提昇信號速度。 此處有兩種主要的電晶體類型：雙極式接合電晶體 (bipolar junction transistors)以及場效電晶體（FET)。雙極式 電晶體係以兩個p-n接合點為基礎，可為n-p-n或p-n-p三 層，構成發射極、基部以及集電器。該主要習知電流係由該 集電器至該發射極，且其不僅取決於該集電器至發射極的電 位差，亦（在正常操作點更為敏感）取決於流經該基部之電流。 而場效電晶體中電流係來自一電流源經過通道而至没 極，其電阻可藉施一電壓至一閘極而控制。於一接面式閘極 場效電晶體（稱JUGFET或JFET)，此係藉p型材料環繞該n 型通道（反之亦然）連接至閘極’該過渡層的寬度控制通道之 電阻。另一種稱為絕緣閘型場效電晶體（稱IGFET)，當施一 200412026 局於臨界之閘極電壓時，該通道會在高摻雜η型源極區及汲 極區間形成Ρ型物質（具有低摻雜濃度）。絕緣閘型場效電晶 體通常為一金氧半導體（MOS)裝置，且因此也稱為金氧半導 體场效電晶體（M0SFET)。取決於製程，m〇sfet亦可分類為 NMOS裝置或pm〇s裝置。 為助於描述本發明，下文將以MOSFET裝置為主，然 熟習此項技術者應瞭解到此處的描述亦同樣適用於其他電 晶體。 第3A圖係表示一 M〇SFET雛型，係以一般符號3〇〇 代表’虽VDS增加時則進一步以模型3〇2表示其變化。換言 之，當通過汲極與源極的電壓增加時，該通道（形狀）3〇4會 開始夾斷。一般來說，該漏極閘電壓係由Vgs設定且不會隨 著vDS改’因此當v〇s增加，Vgd會依據漏極閘電壓 VGD-VGS-VDS而降低，並在低於臨界值時於汲極終點使通道 3 04消失。 第3B圖係表示以第3A圖模型302為基礎之不同寄生 電容器。此等電容器在該信號速度較慢時可忽略，但當信號 速度較快時會變得較為重要。實質上，料電容器是該^ ^ 生效應的主要成因。雖然該等電容器變得較重要時的速度或 頻率並沒有明顯減少，但應可瞭解信號速度越快，寄生效應 也會越明顯。第3C圖係說明一平衡電路模組31〇，其表示當 該信號速度超出某一範圍時會有將假影通過該電路引入= 號中的可能。 10 200412026 本發明之一特徵係將其他原有調整所有因不同寄生電 容（示於第3圖中）所引起之寄生效應的寄生電容量及/或電感 由不同濾波功能引出以強化該信號，並降低該信號所引出的 假影。 依據本發明之一實施例，在一差動放大器或一組差動 放大器中的電晶體係分別經過調整，以使所得的寄生效應可 用於幫助該信號。對一已知的晶圓製程而言，一電晶體的電 容量主要係由MOSFET中該閘極（G)的實體區域或雙極式發 散器來決定。換言之，一電晶體的某一態樣的實體區域在該 實體區域控制流經電晶體的電流時即可決定其寄生電容量。 如此處所述，一描述一電晶體某一態樣實體區域的參 數係定義為一電性等同幾何，其係為一寬及長的函數用以決 定一電晶體某一態樣的實體區域。例如，由一佈局透視圖 中，一關於MOSFET電晶體閘極的實體區域或是一雙極式電 晶體發射極的實體區域。 依據本發明之一實施例，第3D圖係表示一例示性佈局 3 20，其中一 MOSFET裝置322使用九個標準M0SFE丁模型 以製造一放大之MOSFET(事實上為「經放大」之閘極），以 使該MOSFET裝置322的EEG係為一般標準MOSFET模型 路計 電設 或統 器傳 大為 放 皆 動果 差結 在的 置益 引效 置路 裝電 T 或 FE現 OS表 Μ 的 之器 大大 放放 將動 〇 差 大該 倍 ， 九時 的中 的 期 預 法 無 所 能 功 1 或 器 大 放 ^3 差一 内 統 系 路一 於 述 描 於 &C 1B、 為 11 200412026200412026 发明 Description of the invention: [Technical field to which the invention belongs] This case is US Patent Application No. 10/1 1 8,733 filed on April 8, 2002 and US Patent Application No. 1 filed on May 2, 2002 Partial serial application of 10 / 137,988 claims the priority of U.S. Patent Application No. 09 / 947,643 (currently U.S. Patent No. 6,322,595) filed on September 5, 2001, all of which are incorporated herein for reference. The present invention generally relates to the area of integrated circuit design, and particularly relates to the improved design of integrated circuit and its method for high-speed signals. [Previous technology] In the future, the demands of communication networks will increase bandwidth and flexibility due to different communication protocols. Optical fiber networks have been widely used in data transmission due to their high speed and high carrying capacity. Wavelength division multiplexing (WDM) is a technology that puts data from different sources together with each signal carried at the same time on different optical wavelengths on an optical fiber. Using this WDM system, different wavelengths or data channels above 80 can be multiplexed into optical data streams transmitted on a single fiber. It is now expected that the optical data transmission rate contained in a modulated single-mode laser beam on an optical fiber will far exceed 1000 Gbit / sece. At present, the bandwidth of practical optical fiber communication systems is still limited by light. Signal conversion with electronic domain and related electronic hardware. The main component used in current fiber optic communication systems (such as synchronous fiber optic networks) is the optical connector, which is 200412026 combined with transmission / reception in a single _ τ package. Optical connectors can be found in every interface along a fiber optic network, a source, a destination, or a major interface. In addition to optical fiber communication applications, other applications or systems that are intended to use other devices can also use the transceiver to receive or transmit high-speed data, such as wireless communication components. The current connectors used for high-speed 衿 ^ and 15 采用 are made of silicon germanium (SiGe), arsenide (GaAs) scaled steel (Inp) and other processes, but it is still expensive in terms of current technology. The process cost of the scale connector is still not economical. Therefore, there is a need for an alpha meter to be able to manufacture these connectors in a more economical and lower cost manner. [Summary of the Invention] This * section and the abstract of the invention are intended to describe some aspects of the invention, Introducing one or more preferred embodiments. The simplification or omission here is to avoid obscuring the features of this chapter and the summary. However, these simplifications or omissions are not intended to limit the scope of the invention. The present invention relates to the integrated design of differential amplifiers that can be used in many circuits and circuit systems. It is now known that parasitic effects on individual components (such as transistors and resistors) can introduce artifacts into these signals when the frequency of these signals exceeds a certain range. It is an object of the present invention to systematically adjust the components and use the parasitic effect to reduce the artifacts in the beliefs. According to one aspect of the present invention, a parameter defined as Electrically Equivalent Geometry (EEG) is defined as a function of width and length of 200412026, which defines a control of how much current can pass through a portion of the electricity. Crystal. For example, it can be seen from the layout perspective that an EEG is related to the gate region of a MOSFET transistor or the emission region of a bipolar transistor. Properly adjusting the EEG of each transistor in different amplifiers or circuits can reduce these parasitic effects that cause artifacts in the signal, and also form the original resonance filtering function to reduce the harmonic components in the output signal. In order to reduce the artifacts formed by these parasitic effects in the signal or form proper resonance filtering and wave functions, other individual components (such as resistors) can be adjusted systematically. Each of these components is related to a parameter called Electrical Equivalent Component Parameter (EECP), which is also a function that defines the width and length of a semiconductor region for use in manufacturing the component. Properly adjusting the EECP of these components and the EEG of these transistors will not only accommodate higher signal speeds, but also handle higher output signals. To further enhance the ability of a differential amplifier or circuit to accommodate higher signal speeds, inductive components (such as inductors and transformers) are used and systematically adjusted. The inductance from these inductive components will thus reduce the parasitic effects that can cause signal artifacts, giving the differential amplifier or circuit the ability to accommodate higher signal speeds. The present invention still has many advantages and features, one of which is a design method different from the conventional method, so that a differential amplifier or circuit can accommodate those higher signal speeds that cannot be accommodated in the differential amplifier or circuit. . In essence, the present invention can be implemented in high-speed systems, such as processing larger-scale optical fibers 200412026 or wireless communications in a lower-cost semiconductor process (complementary metal oxide semiconductor, 0.18 micron process). Other objects, features, and advantages of the present invention will be more apparent with the accompanying drawings and the preferred embodiments described in detail below. [Embodiment] The present invention relates to the integrated design of a differential amplifier, which can be used in many electronic circuits and systems. It is well known that parasitic effects on individual components (such as transistors and resistors) can introduce artifacts into the signal when the frequency of such signals exceeds a certain range. An object of the present invention is to use the parasitic effect to systematically adjust the components to help reduce the artifacts in the signals. The detailed description of the present invention is presented in the form of procedures, steps, logical blocks, processes or other symbolic expressions, which can directly or indirectly indicate the operation mode of the signal processing device connected to the optical fiber network. These explanations and expressions are those of the person skilled in the art, such as small price & I'm using the pathway. Here, "a specific embodiment" or "a specific embodiment | Situator S_% Mingguan buckle is related to a specific performance, structure or feature described in the specific embodiment, and can be used for 1 ^" Within at least one specific embodiment of the present invention. In this specification, the words "in a specific embodiment" appearing in the rough valleys of the virtual night are not necessarily all referring to the husband and wife. Examples, and individual or alternative specific examples are not mutually exclusive, and are not recognized in other specific examples. Reference is now made to the illustrations in which the same numbers represent the same elements in all the drawings. Figure 1A is an example of an illustrative adapter 100 that can be used in an optical fiber network by Yu Riyi and Yu Tian. The transceiver 100 includes two functional blocks, a receiver 102 and a transmitter 104. _ Optical-to-electrical converter 103 (such as a photodiode 200412026 body) converts these optical signals into electronic signals and is received by the receiver 102. The electronic signal is amplified by a conversion resistance amplifier (TIA) 106, and further amplified by a limiting amplifier 108 to an appropriate signal range. Behind the limiting amplifier 108 is a clock data recovery (CDR) circuit 1 10, which includes a phase-locked loop (PLL). It is not shown here that the signal amplified by the limiting amplifier is locked. The information in the form of electronic signals and the clock information therein will be replied. A DeMUX 11 2 is used to demultiplex the data to maintain multiple channels, such as OC-3 (155Mbits / s), OC-12 (622Mbits / S), and OC-48 (24 8 8Mbits / s) . At the other end, the transmitter includes a MUX 118 that can multiplex signals from several channels to obtain a signal that can pass through other circuits 116 before reaching a driver 114 to provide the signals to a light. _ Electric converter 103 (for example, a laser generator). FIG. 1B shows an exemplary connector 130 that can be used for wireless communication components. The transceiver 130 may also include two functional blocks, a receiver 132 and a transmitter 134. The receiver 132 receives an electronic signal from an antenna 13 3, and the electronic signal is then amplified to a certain strength in a low noise amplifier 丨 36, and the amplified signal is then combined with a mixer 138 and a The oscillating signals from the oscillator 135 are mixed, and then one or more signals suitable for subsequent analog-digital processing are rotated out. In an application, the mixer i 3 8 can perform the function of a down-converter to receive the 49GHz 仏 signal from the oscillator 135. At the other end, the transmitter 134 receives the data and modulates the data in an amplitude modulator " ο. The modulated signal is up-converted in an inverter 142 to match the oscillating signal from the oscillator 135, and is further amplified in a power amplifier 144 before reaching the antenna 133 for transmission. 200412026 Other applications or systems that also use the adapter are not listed here. In Figure 1A or 1B, the speed at which the adapter processes these passing signals has a profound impact on the optical fiber network or wireless communication components. To ensure that the transceiver can process high-speed signals (such as 40GHz or 100 Mbits / second speed), each functional block in the transceiver must be able to process the signal speed without introducing artifacts into the signals. Many functional or building blocks now use differential inputs to improve performance. Generally, before passing through an analog-to-digital conversion, circuit components such as amplitude, impedance matching, filtering, and level shifting are used, and one or more differential amplifiers or circuits are used. It should be understood that a complete differential circuit can not only meet these conditions, but also effectively simplify the design task. In addition, designs that can match the characteristics of the same 7L pieces on the same substrate will heavily use symmetry as a filtering mechanism. The configuration of the differential amplifier circuit is particularly important in this aspect. Referring now to FIG. 2, it shows a differential circuit 200 including three differential amplifiers 202, 204, and 206 (the details of these differential amplifiers 206 are not shown), and the differential amplifiers are Coupling in a way that is commonly found in functional blocks—connectors or other circuits. It should be expected that a current source 208 provides the desired current I, and those skilled in the art should understand that one-half the current I can drive each amplifier 202 or 206, so only 1/2 The current I passes through the transistors T3 and T4. In the case of the amplifier 202, it is driven by a current I of 1/2 (by the amplifier 204) and therefore a current I of 4/4 is passed through the transistors T1 and T2. In the design of conventional technology, these transistors T1 or T2 and T3 or T4 are generally designed according to the proportion of current passing. 200412026 However, when the speed of the signal passing through the circuit 200 increases, the parasitic effect will begin to play a role of distorting the signal. At this time, if the circuit 200 is still designed and implemented in a conventionally used method, it will therefore limit the circuit 200 can handle Hold the speed. It is worth noting that in addition to the conventional method, the present invention is to expose and adjust the parasitic effect, and to establish the technology of resonance effect to provide filtering function to the artifacts introduced by the parasitic effect formed by the South Speed signal. fight". According to an aspect of the present invention, various transistor systems are adjusted to relatively increase / decrease corresponding to the parasitic capacitance, so that the parasitic effects and resonance effects of the inherent filtering can be effectively and smoothly used. According to another aspect of the present invention, several inductors are used to further reduce the parasitic effects that cause artifacts, and form more appropriate resonance effects to further increase the signal speed. There are two main types of transistors here: bipolar junction transistors and field-effect transistors (FETs). The bipolar transistor system is based on two p-n junctions, which can be three layers of n-p-n or p-n-p, which form the emitter, base, and current collector. The main known current is from the current collector to the emitter, and it depends not only on the potential difference from the current collector to the emitter, but also (more sensitive at normal operating points) depending on the current flowing through the base. In the field effect transistor, the current comes from a current source through the channel to the anode, and its resistance can be controlled by applying a voltage to a gate. In a gate-type field-effect transistor (referred to as a JUGFET or JFET), this is a p-type material that surrounds the n-type channel (and vice versa) and connects to the gate ’s width of the transition layer to control the resistance of the channel. The other type is called an insulated gate field effect transistor (known as IGFET). When a 200412026 is applied at a critical gate voltage, the channel will form a P-type material in the highly doped n-type source region and the drain region ( With low doping concentration). The insulated gate field effect transistor is usually a metal-oxide-semiconductor (MOS) device, and is therefore also referred to as a metal-oxide semiconductor field-effect transistor (MOSFET). Depending on the process, mfsfet can also be classified as an NMOS device or a pmos device. In order to help describe the present invention, the following will mainly focus on MOSFET devices, but those skilled in the art will understand that the description here is also applicable to other transistors. Figure 3A shows a prototype of a MOSFET, which is represented by the general symbol 300. Although the VDS increases, the change is further represented by the model 302. In other words, when the voltage across the drain and source increases, the channel (shape) 304 starts to pinch off. Generally, the drain gate voltage is set by Vgs and will not change with vDS. Therefore, when v0s increases, Vgd will decrease according to the drain gate voltage VGD-VGS-VDS, and when it is lower than the critical value At the end of the drain, channel 3 04 disappears. Fig. 3B shows different parasitic capacitors based on the model 302 of Fig. 3A. These capacitors can be ignored when the signal speed is slower, but become more important when the signal speed is faster. In essence, the capacitor is the main cause of this effect. Although the speed or frequency at which these capacitors became more important did not decrease significantly, it should be understood that the faster the signal speed, the more pronounced the parasitics. Figure 3C illustrates a balanced circuit module 31o, which indicates that when the signal speed exceeds a certain range, there is a possibility that an artifact will be introduced into the = sign through the circuit. 10 200412026 One of the features of the present invention is to adjust the other original parasitic capacitances and / or inductances of all parasitic effects caused by different parasitic capacitances (shown in Figure 3) from different filtering functions to strengthen the signal, and Reduce the artifacts from this signal. According to an embodiment of the present invention, the transistor system in a differential amplifier or a group of differential amplifiers is individually adjusted so that the resulting parasitic effect can be used to assist the signal. For a known wafer process, the capacitance of a transistor is mainly determined by the solid area of the gate (G) in the MOSFET or a bipolar radiator. In other words, the physical area of a certain aspect of a transistor can determine its parasitic capacitance when the solid area controls the current flowing through the transistor. As described herein, a parameter system describing a solid region of a transistor is defined as an electrical equivalent geometry, which is a wide and long function used to determine a solid region of a transistor. For example, from a layout perspective, a physical area of a MOSFET transistor gate or a bipolar transistor emitter of a physical region. According to an embodiment of the present invention, the 3D diagram shows an exemplary layout 3 20, in which a MOSFET device 322 uses nine standard MOSFET models to make an amplified MOSFET (actually an "amplified" gate). In order to make the EEG of the MOSFET device 322 be a general standard MOSFET model circuit meter or device, it is a device that can be used to improve the performance of the MOSFET device T or FE. It will be greatly increased, the difference will be large, the time will be doubled, the mid-term period is 9: 1, or the device will be released ^ 3. The difference between the internal system and the road is described in &
•電性等同元件參數（EECP)亦同樣定義如下 電阻之EECP =其電阻值； 電感元件之EECP值=其電感值； EECP值=該電感元件間個 於輕合電感元件内變壓器之EECP補=姑發 別電感值以及耦合係數組成之向量； 一電容元件之EECP值=其電容值；以及 一電阻器之EECP值=其EEG值 透過上述疋義，可更有效的描述並讓該些熟習此項技 術人士瞭解本發明。第4圖係表示一使用數個差動放大器（例 如M1M2、M3M4以及M5M6)的除以2除法器之例示性電路 400。Vcs係一施於該等電晶體MC1及MC2之閘極的偏壓， 用以設定一預定量的電流以供應該等差動放大器。通過該除 法器400，施於CLK 402及CLKb 402間的差動信號頻率將 會被除以二，且所得信號會由q3 406及Q3b 408輸出。 依據本發明之另一實施例，該電路4〇〇或其中該些差 動放大器的設計儘管在電路拓樸上仍有些相似處，但卻與習 知技術大不相同。第5A圖係表示可用於第4圖中該電路400 中或其他建構區塊中的差動放大器或電路之設計流程或步 驟5 00。於流程502中係決定通過每一電晶體的最初電流量。 通過一電晶體之電流量可依據第2圖中之例示判定之。 於流程504中，該輸入電晶體（例如第2圖中的T3及 T4、第4圖中的Ml及M2)的EEG係分別經調整以使之在差 12 200412026 動放大器或電路相對於其頻率皆正常工作的條件下接近最 小值。此一目的係確保藉由經微小化的電晶體將該寄生效應 降至最低。第5Β圖表示一例示性電晶體佈局52〇，其表示一 由一 EEG(寬度W及長度L的函數）所決定之閘極區域522。 一經「微小化」之電晶體可指出該EEG的值係在未影響預期 會通過該閘極5 2 2之電流而降至最低。應可瞭解的是，含兮 E G G值係最微小時，該些由於一高頻信號使電晶體所導致的 寄生效應亦會降至最低。 於流程506中，該差動放大器或電路中剩餘的ΕΕ〇值 可經調整以使該等輸出信號的諧波分量降至最低。此方式明 顯與習知技術相異的是’習知技術是利用經「微小化」之電 晶體使該些寄生效應降至最低，然本發明是改變用於其餘電 晶體之EEG的比值使該些寄生效應降至最低。例如，就第2 圖中該等電晶體T1及T2而言，其EEG比值（例如T1的EEG 除以T2的EGG)便不再是一。依據本發明之一實施例，兮比 值係大於一「定值」。如第5B圖中所示，當放大一電晶體 的寬或長、且縮小另一電晶體的寬或長時（在不影響通過電流 量的情況下），相關的寄生電容量會相對的被改變。連同該來 自其他經調整電晶體經改變的寄生電容量，該等實施例已證 明輸出馆號的質至少因兩個理由而有明顯的改善，第一，所 有寄生電容量都經過調整而有利於該信號，其中某些會對該 信號形成假影的寄生電容量也都由於連續連接若干入成寄 生電容器的特性而降低。第二，來自原本諧振電路的若干寄 13 200412026 生電容器與其他寄生元件在其值經適當調整時，將可提供所 欲的濾波功能。 於流程508中，該等輸出信號係經檢視。若該等輸出 信號有經充分評估，該處理步驟5〇〇會終止。若該等輸出信 號未作充分評估，該處理步驟5〇〇會進行至流程51〇。一般 而言，當該等信號的頻率通過本發明之該等差動放大器未超 過某一範圍時，該等差動放大器會傳送出最後的信號，且此 七號的品質也優於同樣條件下的習知技術所送出的信號。當 該等信號頻率超出一範圍時，額外的設計會在流程51〇處進 行評估。 於流程510處’於該差動放大器中其他元件的eecp• Electrically equivalent component parameters (EECP) are also defined as follows: EECP of the resistance = its resistance value; EECP value of the inductive component = its inductance value; EECP value = EECP compensation of the transformer between the inductive component and the light-duty inductance component = Give a vector consisting of the inductance value and the coupling coefficient; the EECP value of a capacitive element = its capacitance value; and the EECP value of a resistor = its EEG value. Through the above meanings, we can more effectively describe and let those familiar with this Those skilled in the art understand the present invention. Figure 4 shows an exemplary circuit 400 of a divide-by-2 divider using several differential amplifiers (e.g., M1M2, M3M4, and M5M6). Vcs is a bias voltage applied to the gates of the transistors MC1 and MC2 to set a predetermined amount of current to supply the differential amplifiers. With this divider 400, the frequency of the differential signal applied between CLK 402 and CLKb 402 will be divided by two, and the resulting signal will be output by q3 406 and Q3b 408. According to another embodiment of the present invention, although the design of the circuit 400 or the differential amplifiers is similar in circuit topology, it is quite different from the conventional technology. Figure 5A shows the design flow or step 500 of a differential amplifier or circuit that can be used in the circuit 400 or other building blocks of Figure 4. In process 502, the initial amount of current through each transistor is determined. The amount of current passing through a transistor can be determined based on the illustration in Figure 2. In process 504, the EEG of the input transistor (for example, T3 and T4 in Figure 2 and Ml and M2 in Figure 4) are adjusted to make the difference 12 200412026 the amplifier or circuit relative to its frequency It is close to the minimum value under normal operating conditions. This purpose is to ensure that parasitic effects are minimized by miniaturized transistors. FIG. 5B shows an exemplary transistor layout 52, which shows a gate region 522 determined by an EEG (a function of width W and length L). Once "miniaturized" the transistor can point out that the value of the EEG is minimized without affecting the current expected to pass through the gate 5 2 2. It should be understood that the E G G value is the smallest, and the parasitic effects caused by the transistor due to a high-frequency signal will also be minimized. In process 506, the remaining EO value in the differential amplifier or circuit can be adjusted to minimize the harmonic components of the output signals. This method is obviously different from the conventional technology. 'The conventional technology uses the "miniaturized" transistor to minimize these parasitic effects. However, the present invention is to change the ratio of EEG used for the remaining transistors to make the These parasitic effects are minimized. For example, for the transistors T1 and T2 in Figure 2, the EEG ratio (such as the EEG of T1 divided by the EGG of T2) is no longer one. According to an embodiment of the present invention, the ratio of Xi is greater than a "fixed value". As shown in Figure 5B, when the width or length of one transistor is enlarged and the width or length of the other transistor is reduced (without affecting the amount of passing current), the related parasitic capacitance will be relatively change. Together with the altered parasitic capacitance from other adjusted transistors, these examples have demonstrated that the quality of the output hall number has improved significantly for at least two reasons. First, all parasitic capacitances have been adjusted to facilitate The parasitic capacitance of this signal, some of which will cause artifacts to the signal, are also reduced due to the characteristics of continuous connection of several parasitic capacitors. Second, some capacitors and other parasitic elements from the original resonant circuit will provide the desired filtering function when their values are properly adjusted. In process 508, the output signals are reviewed. If these output signals are fully evaluated, this processing step 500 will be terminated. If these output signals are not fully evaluated, the processing step 500 will proceed to flow 51. Generally speaking, when the frequency of these signals does not exceed a certain range through the differential amplifiers of the present invention, the differential amplifiers will transmit the final signal, and the quality of this number 7 is better than under the same conditions The signals sent by the conventional technology. When these signal frequencies are outside a range, additional designs are evaluated at Process 51. At flow 510 ’on the eecp of other components in the differential amplifier
值係分別調整以進一步降低該輸出信號中的諧波分量。第5C 圖係表示一電阻佈局5 3 〇之例示透視圖。該電阻器之電阻值 係由相關之EECP所控制，且亦為寬度w及長度乙的函數。 依據本發明之一實施例，該電阻器之Eecp值係分別調整以 進步平衡通過對應電晶體之電流，以得不同電阻器不同的 EECP 值。 於流程5 12處，該等輸出信號係經檢視，若該等輸出 仏號有經充分評估，該處理步驟500會終止。若該等輸出信 號未作充分評估，該處理步驟5〇〇會進行至流程514，由於 該仏號逮度的強度，其可指出該等明顯可能之寄生效應處。 於流程514處，係採用該等電感元件以進一步調整該 些寄生效應’並形成更有效率或更適當的諧振濾波功能以強 14 200412026 化通過該電路的信號。依據本發明之一實施例，係加入數個 電感器並串聯式的分別與該等電阻器相耦接。如第5D圖所 示一交互捲繞之變壓器540(包括兩個電感器）之例示性佈局 亦有一寬度W與長度L的函數EECP，該寬度W係指瘦長條 狀物542或544的寬度，且長度L係指該瘦長條狀物542或 544的總長。為進一步利用該電感器，係以每兩個電阻器為 一對進行配置以形成一變壓器，且該變壓器具有一可藉調整 該兩個電感器之配置而決定之耦合係數。第6圖係表示改良 第4圖之一電路，其包括該經採用之電感器（一對電感器形成 之一變壓器）。 ’ 為容納該高頻信號，該電感元件（例如電感器）係分別調 整EECP的值以使該輸出信號的諧波分量可進一步減小。根 本上，該電感量有助於降低若干寄生效應，且另方面來說， 也有利於形成更適當之諳振效果以提供較佳的濾波功能。 習之技術之差動放大器或電路為高的頻率。當該等本發明之 差動放大器或電路用於-系統（例如-接收nm，其應可理 解的是該系統也可容納很高的信號速度。於本發明之一應用 中於第4圖或第6圖中包括該等依據本發明設計之差動放 大器的差動電路可用於S 向 、第7A圖所示之建構區塊700。尤其 疋兩輸出702 * 704分別對應帛6圖之clk 6〇2以及 604’且兩輸出706 * 7〇8分別對應第6圖的…儀及⑽ 608因此卜對頻率為f的差動信號施於該等輸出Μ 15 200412026 及704時，該等輸出706及708將會輸出頻率為F/2的合成 信號。 第7B圖係表示四個上述串聯連結之建構區塊，以使信 號頻率減少16倍。換言之，當一對頻率為F的差動信號施 於該等輸入718及720時，該等輸出722及724將輸出頻率 為F/16的合成信號。下列四個表格係分別表示使用第6圖的 電路600作為建構區塊之對應元件的設計。 表1 :用於第7B圖除法器710之EEC P的設計 元件 EECP 單位 EECP之比值 R3 25 歐姆 1.667 R4 25 歐姆 1.667 R13 15 歐姆 1.000 R14 15 歐姆 1.000 L3 250 兆分之一亨利(picohenry) 16.667 L4 250 兆分之一亨利(picohenry) 16.667 L13 180 兆分之一亨利(picohenry) 12.000 L14 180 兆分之一亨利(picohenry) 12.000 K34 0.5 無單位 0.033 K134 0.5 無單位 0.033 MCI 260 無單位 17.333 MC11 260 無單位 17.333 Ml 160 無單位 10.667 16 200412026 M2 160 無 單 位 10.667 Mil 160 無 單 位 10.667 M12 160 無 單 位 10.667 M3 160 無 單 位 8 • 000 M4 120 無 單 位 8 • 000 M5 170 無 單 位 1 1.333 M6 170 無 單 位 1 1.333 M13 140 無 單 位 9 • 333 M14 140 無 單 位 9 • 333 M15 170 無 單 位 1 1.333 M16 170 無 單 位 1 1.333The values are adjusted separately to further reduce the harmonic components in the output signal. Figure 5C is an exemplary perspective view showing a resistor layout 5 3 0. The resistance of this resistor is controlled by the relevant EECP and is also a function of width w and length B. According to an embodiment of the invention, the Eecp value of the resistor is adjusted separately to improve the balance of the current passing through the corresponding transistor to obtain different EECP values for different resistors. At process 5 12, the output signals are reviewed. If the output signals are fully evaluated, the processing step 500 will be terminated. If the output signals have not been fully evaluated, the processing step 500 will proceed to flow 514. Due to the intensity of the signal, it can indicate the obvious possible parasitic effects. At flow 514, the inductive elements are used to further adjust the parasitic effects ' and form a more efficient or more appropriate resonant filtering function to strengthen the signal passing through the circuit. According to an embodiment of the present invention, a plurality of inductors are added and coupled in series with the resistors, respectively. As shown in FIG. 5D, the exemplary layout of an alternately wound transformer 540 (including two inductors) also has a function EECP of a width W and a length L. The width W refers to the width of the thin strip 542 or 544. And the length L refers to the total length of the elongated strip 542 or 544. To further utilize the inductor, every two resistors are configured as a pair to form a transformer, and the transformer has a coupling coefficient that can be determined by adjusting the configuration of the two inductors. Fig. 6 shows an improved circuit of Fig. 4 including the used inductor (a transformer formed by a pair of inductors). ’To accommodate the high-frequency signal, the inductive element (such as an inductor) adjusts the value of EECP separately so that the harmonic component of the output signal can be further reduced. Basically, the amount of inductance helps to reduce several parasitic effects, and on the other hand, it also helps to form a more appropriate vibration effect to provide a better filtering function. The difference technology or circuit of the conventional technology is high frequency. When the differential amplifier or circuit of the present invention is used in a system (eg, receiving nm), it should be understood that the system can also accommodate very high signal speeds. One application of the present invention is shown in FIG. 4 or The differential circuit including the differential amplifier designed according to the present invention in FIG. 6 can be used in the S-direction and the building block 700 shown in FIG. 7A. In particular, the two outputs 702 * 704 correspond to clk 6 in FIG. 6 respectively. 〇2 and 604 'and the two outputs 706 * 7〇8 correspond to ... and ⑽ 608 in Figure 6, respectively. Therefore, when the differential signal with frequency f is applied to these outputs M 15 200412026 and 704, these outputs 706 And 708 will output a composite signal with a frequency of F / 2. Figure 7B shows the four building blocks connected in series to reduce the signal frequency by 16 times. In other words, when a pair of differential signals with a frequency of F is applied At these inputs 718 and 720, the outputs 722 and 724 will output a composite signal with a frequency of F / 16. The following four tables show the design of the corresponding components using the circuit 600 of Fig. 6 as a building block, respectively. Table 1: Design Elements EECP for EEC P of Divider 710 in Figure 7B Unit EECP ratio R3 25 ohms 1.667 R4 25 ohms 1.667 R13 15 ohms 1.000 R14 15 ohms 1.000 L3 250 picohenry 16.667 L4 250 picohenry 16.667 L13 180 megahenry ( picohenry) 12.000 L14 180 picohenry 12.000 K34 0.5 unitless 0.033 K134 0.5 unitless 0.033 MCI 260 unitless 17.333 MC11 260 unitless 17.333 Ml 160 unitless 10.667 16 2004 12026 M2 160 unitless 10.667 Mil 160 unitless 10.667 M12 160 without units 10.667 M3 160 without units 8 • 000 M4 120 without units 8 • 000 M5 170 without units 1 1.333 M6 170 without units 1 1.333 M13 140 without units 9 • 333 M14 140 without units 9 • 333 M15 170 without units 1 1.333 M16 170 unitless 1 1.333
表2 :用於第7B圖除法器712之EECP的設計 元件 EECP 單位 EECP 之 R3 90 歐姆 1.500 R4 90 歐姆 1.500 R13 60 歐姆 1.000 R14 60 歐姆 1.000 L3 850 兆分之一亨利(picohenry) 14.167 L4 850 兆分之一亨利(picohenry) 14.167 L13 750 兆分之一亨利(picohenry) 12.500 L14 750 兆分之一亨利(picohenry) 12.500 K34 0.5 無單位 0.008 K134 0.5 無單位 0.008Table 2: Design elements of EECP for divider 712 in Figure 7B EECP unit R3 90 ohms 1.500 R4 90 ohms 1.500 R13 60 ohms 1.000 R14 60 ohms 1.000 L3 850 picohenry 14.167 L4 850 trillion Phenhenry 14.167 L13 750 Phihenry 12.500 L14 750 Phihenry 12.500 K34 0.5 No unit 0.008 K134 0.5 No unit 0.008
17 200412026 MCI 240 無單位 4.000 MCI 1 240 無單位 4.000 Ml 120 無單位 2.000 M2 120 無單位 2.000 Mil 120 無單位 2.000 M12 120 無單位 2.000 M3 150 無單位 2.500 M4 150 無單位 2.500 M5 180 無單位 3.000 M6 180 無單位 3.000 Ml 3 140 無單位 2.333 M14 140 無單位 2.333 M15 160 無單位 2.667 M16 160 無單位 2.667 表3 : 用於第7B圖除法器714之EECP的設計 元件 EECP 單位 EECP之比值 R3 200 歐姆 0.667 R4 200 歐姆 0.667 R13 300 歐姆 1.000 R14 300 歐姆 1.000 L3 0 兆分之一亨利(picohenry) 0.000 L4 0 兆分之一亨利(picohenry) 0.000 L13 0 兆分之一亨利(picohenry) 0.00017 2004 12026 MCI 240 without unit 4.000 MCI 1 240 without unit 4.000 Ml 120 without unit 2.000 M2 120 without unit 2.000 Mil 120 without unit 2.000 M12 120 without unit 2.000 M3 150 without unit 2.500 M4 150 without unit 2.500 M5 180 without unit 3.000 M6 180 Unit-free 3.000 Ml 3 140 Unit-free 2.333 M14 140 Unit-free 2.333 M15 160 Unit-free 2.667 M16 160 Unit-free 2.667 Table 3: Design Elements for EECP for Divider 714 in Figure 7B EECP Ratio of Unit EECP R3 200 Ohm 0.667 R4 200 ohms 0.667 R13 300 ohms 1.000 R14 300 ohms 1.000 L3 0 picohenry 0.000 L4 0 picohenry 0.000 L13 0 picohenry 0.000
18 200412026 L14 K34 K134 MCI MCI 1 Ml M2 Mil Ml 2 M3 M4 M5 M6 M13 M14 M15 M16 表4 : 元件 R3 R4 R13 R14 0 兆分之一亨利(picohenry) 0. ,000 0 無 單 位 0. ,000 0 無 單 位 0.000 240 無 單 位 0. • 800 240 無 單 位 0. ,8 00 100 無 單 位 0_ ,333 100 無 單 位 0. ,333 100 無 單 位 0_ ,333 100 無 單 位 0. ,333 80 無 單 位 0_ ,267 80 無 單 位 0_ .267 90 無 單 位 0, ,300 90 無 單 位 0 .300 80 無 單 位 0 .267 80 無 單 位 0 .267 90 無 單 位 0 • 300 90 無 單 位 0 • 300 於第7B圖除法器716之EE CP的設計 EECP 單位 250 歐姆 250 歐姆 250 歐姆 250 歐姆 EECP之比值 1.000 1.000 1.000 1.000 19 200412026 L3 0 兆分之一亨利(picohenry) 0.000 L4 0 兆分之一亨利(picohenry) 0.000 L13 0 兆分之一亨利(picohenry) 0.000 L14 0 兆*分之一亨利(picohenry) 0.000 K34 0 無單位 0.000 K134 0 無單位 0.000 MCI 180 無單位 0.720 MCI 1 180 無單位 0.720 Ml 80 無單位 0.320 M2 80 無單位 0.320 Mil 80 無單位 0.320 M12 80 無單位 0.320 M3 100 無單位 0.400 M4 100 無單位 0.400 M5 150 無單位 0.600 M6 150 無單位 0.600 M13 100 無單位 0.400 M14 100 無單位 0.400 M15 150 無單位 0.600 M16 150 無單位 0.600 為便於暸解本發明及上述表格，表1的某些元件值係 表列如下： 電阻器R3=25歐姆 20 200412026 電阻器R14=15歐姆 電感元件L1 3 = 1 80兆分之一亨利（1 〇-12亨利） 電感元件L14 = 1 80兆分之一亨利（1 〇·12亨利） K134 = L13及L14間的耦合係數=〇.5(無單位） 電晶體Mcl有260(無單位）的EECG 電晶體Ml有160(無單位）的EECG 因此，該對應的「EECP比值」便可由下而得： 25:15:180:180:0.5:260:160=1.667:1.〇〇〇: 12.000:12.000:0.033:17.333:10.667 在得到上列的EECP比值後，便可作出將該R14的 EECP當作公約數的選擇。一般而言，只要所得的EECP比值 易於表示，這樣的選擇都可任意決定。 由上列表格應可注意到該等除法器7丨〇、7 12、7 1 4及 716每一個都有一組比值，且每組比值都與其他組不相同。 如此處所用者’一組比值係稱為一共用因數值（或稱公因子， Common Factor，CF)，其用以定義比值矩陣或比值向量（若所 有比值都置於一攔時）。因此，如同本發明之一特徵，一用於 一除法器（例如710)的CF便與用於另一組除法器的（例如 712)CF不相同。 應注思的疋，一般上列表格中缺少電容元件的 時，對該等熟習此項技術人士而言，應可瞭解許多電容元件 對EECP的調整值都已内含於本發明中。這是因為該間極、 源極 '汲極以及一建構區塊内的多數電晶體之中含有原有的 電容70件’且此等電容元件的EECp在按照每—特定電曰曰體 的EEG調整下都會有所變化。 θ9 21 200412026 第7A及7B圖係使用一或多個依據本發明設計之差動 放大器之該等電路的例示❶該些熟悉此項技術者應可瞭解本 發明亦可應用在其他電子系統中，包括但不限於：2.5Gbit/sec 的光纖通訊網路（OC48)、10 Gigabit的乙太網路以及40 Gbit/sec(OC768)的傳輸率、超高速乙太網路、1〇 Gigabit超 高速乙太網路、藍芽技術（2·4 GHz)以及無線區域網路（5.2 GHz)，因此，藉由本發明，用於高速資料處理的硬體建設將 成為可能。 在已知本文說明後，該等熟習此項技術者應可暸解本 ^明之電路設計所提供容納高速信號的解決之道，不會因為 日日圓製程（如0.25/zm、0.18//m或〇·〇9μιη)而有製造上的限 制。事實上，在晶圓製程的持續發展下，本發明之方法亦能 ，持續其微小化的過程以達更高速的運算。 本發明已充分描述如上，然該等熟習此項技術者應暸 解的是，本發明係藉由舉例以揭示實施例，且在元件排列或 、、且口上的改變皆不應悖離本發明所主張之申請專利範圍。因 此，本發明之範圍之範圍應以後述之申請專利範圍為主，而 非前述所描述之該等實施例。 【圖式簡單說明】 本發明此等及其他特徵、態樣以及優點在參照下文說 月附加圖不以及申睛專利範圍後將可進一步了解，其中： 第1Α圖係說明可用於一光纖網路中之一例示性傳接 器； 22 200412026 第1B圖係表示可用於一無線通訊元件之一例示性傳 接器； 第2圖係表示一包含三個差動放大器之電路，其係以 常見於功能性區塊中建立一傳接器或其他電路的方式作耦 接； 第3A圖係以一般使用的記號表示之m〇SFet模型， 其更以一製程模型中，當VDS增加，一電流通道於汲極端開 始夾斷（pinch-off)時來表示； 第3B圖係表示以第3A圖之製程模型為主之各種寄生 電容器； 第3C圖係說明一平衡電路模型，其顯示當該信號速度 超出某一範圍時已有將該些假影引入通過該電路信號中的 可能； 第3D圖係表示一例示性佈局，其中一 M0SFET元件 使用九個標準M0SFET模組以製造較大之m〇SFET(實際上 放大之閘極）以使該M0SFET元件之EEG較一般M0SFET模 組大九倍； 第4圖係表不一使用數個差動放大器之除以2除法器 的典型電路架構； 第5A圖係表示可用於第4圖之電路架構的該等差動放 大器或電路之設計流程或步驟； 第5B圖係表示由一 EEG(寬W且長L之一函數）決定 的閘極區域之例示性電晶體佈局. 23 200412026 第5C圖係表示一電阻佈局之例示性透視圖； 第5D圖係表示一交互捲繞變壓器之例示性佈局； 第6圖係表示第4圖包含電感器之一改良電路； 第7A圖係表示一符號或標記，包含依據本發明設計之 差動放大器且可作為一建構區塊；以及 第7B圖係表示四個上述建構區塊，其係連續連結以降 低除以1 6之訊號頻率。 【元件代表符號簡單說明】 102 接收器 103 光-電轉換器 104 傳送器 106 轉換電阻放大器 108 限輻放大器 110 時脈&實料回復（CDR) 114 驅動器 116 其他電路 130 傳接器 133 天線 1 3 6 低雜訊放大器 138 混頻器 135 震盪器 144 電源放大器 142 升頻變頻器 24 200412026 140 調 變 器 200 差 動 電 路 202 差 動 放 大 器 204 差 動 放 大 器 206 差 動 放 大 器 208 電 流 源 302 模 型 310 平 衡 電 路 模 組 320 例 示 性 佈 局 322 MOSFET 裝 置 400 例 示 性 電 路 520 例 示 性 電 晶 體佈局 522 閘 極 區 域 530 例 示 性 電 阻 540 變 壓 器 542 條狀物 544 條狀物 600 電路 702、718 輸入 704、720 輸入 706 、 722 輸出 708 、 724 輸出 2518 200412026 L14 K34 K134 MCI MCI 1 Ml M2 Mil Ml 2 M3 M4 M5 M6 M13 M14 M15 M16 Table 4: Components R3 R4 R13 R14 0 picohenry 0. 0 0 0 0 0 0 0 0 0 0 Unitless 0.000 240 Unitless 0. • 800 240 Unitless 0., 8 00 100 Unitless 0_, 333 100 Unitless 0., 333 100 Unitless 0_, 333 100 Unitless 0., 333 80 Unitless 0_, 267 80 Unitless 0_ .267 90 Unitless 0,, 300 90 Unitless 0 .300 80 Unitless 0 .267 80 Unitless 0 .267 90 Unitless 0 • 300 90 Unitless 0 • 300 in Figure 7B Divider 716 Design of EE CP EECP unit 250 ohm 250 ohm 250 ohm 250 ohm EECP ratio 1.000 1.000 1.000 1.000 19 2004 12026 L3 0 picohenry 0.000 L4 0 picohenry 0.000 L13 0 trillion One henry (picohenry) 0.000 L14 0 trillion * one thousandth henry (picohenry) 0.000 K34 0 unitless 0.000 K134 0 unitless 0.000 MCI 180 unitless 0.720 MCI 1 180 unitless 0.720 Ml 80 unitless 0.320 M2 80 unitless 0.320 Mil 80 unitless 0.320 M12 80 unitless 0.320 M3 100 unitless 0.400 M4 100 unitless 0.400 M5 150 unitless 0.600 M6 150 unitless 0.600 M13 100 unitless 0.400 M14 100 unitless 0.400 M15 150 unitless 0.600 M16 150 unitless 0.600 In order to facilitate understanding of the present invention and the above table, some component values of Table 1 are listed as follows: Resistor R3 = 25 ohms 20 200412026 Resistor R14 = 15 ohms Inductive element L1 3 = 1 80 trillion henries (1 〇 -12 Henry) Inductive element L14 = 1 Henry per 80 trillion (10.12 Henry) K134 = Coupling coefficient between L13 and L14 = 0.5 (unitless) Transistor Mcl has 260 (unitless) EECG The transistor M1 has an EECG of 160 (no unit). Therefore, the corresponding "EECP ratio" can be obtained from: 25: 15: 180: 180: 0.5: 260: 160 = 1.667: 1.〇〇〇: 12.000: 12.000: 0.033: 17.333: 10.667 After getting the EECP ratio listed above, you can choose to use the R14 EECP as the common divisor. In general, as long as the obtained EECP ratio is easy to express, such selection can be arbitrarily determined. It should be noted from the above list that each of these dividers 7 丨 0, 7 12, 7 1 4 and 716 has a set of ratios, and each group is different from the other groups. As used herein, a group of ratios is called a common factor (or Common Factor, CF), which is used to define a ratio matrix or a ratio vector (if all ratios are placed in a block). Therefore, as a feature of the present invention, a CF for one divider (e.g., 710) is different from a CF for another set of dividers (e.g., 712). It should be noted that in the absence of a capacitive element in the list, for those skilled in the art, it should be understood that the adjustment value of EECP for many capacitive elements is included in the present invention. This is because the intermediate electrode, the source 'drain, and the majority of the transistors in a building block contain the original capacitors of 70 pieces', and the EECp of these capacitive elements are in accordance with the EEG of each specific electrical system. There will be changes under the adjustment. θ9 21 200412026 Figures 7A and 7B are examples of these circuits using one or more differential amplifiers designed according to the present invention. Those skilled in the art should understand that the present invention can also be applied to other electronic systems. Including but not limited to: 2.5Gbit / sec optical communication network (OC48), 10 Gigabit Ethernet and 40 Gbit / sec (OC768) transmission rates, ultra-high-speed Ethernet, 10Gigabit ultra-high-speed Ethernet Internet, Bluetooth technology (2.4 GHz), and wireless local area network (5.2 GHz). Therefore, with the present invention, hardware construction for high-speed data processing will become possible. After knowing the description of this article, those familiar with this technology should understand the solution provided by the circuit design of this document to accommodate high-speed signals, not because of the Japanese yen process (such as 0.25 / zm, 0.18 // m, or 〇). 〇9μηη) and there are manufacturing restrictions. In fact, under the continuous development of the wafer process, the method of the present invention can also continue its miniaturization process to achieve higher speed operations. The present invention has been fully described as above, but those skilled in the art should understand that the present invention discloses the embodiments by way of example, and the changes in the arrangement of the elements or the mouth should not deviate from the present invention. Claimed scope of patent application. Therefore, the scope of the present invention should be based on the scope of patent application described later, rather than the embodiments described above. [Brief description of the drawings] These and other features, aspects, and advantages of the present invention will be further understood after referring to the appended drawings and patent scope of the patent, where: Figure 1A illustrates that it can be used in an optical fiber network One example of an exemplary connector; 22 200412026 Figure 1B shows an exemplary connector that can be used for a wireless communication component; Figure 2 shows a circuit containing three differential amplifiers, which is commonly used in A connector or other circuit is established for coupling in the functional block. Figure 3A is a mSFet model represented by commonly used symbols. It is also a process model. When VDS increases, a current channel It is shown when the drain terminal starts pinch-off; Figure 3B shows various parasitic capacitors based on the process model of Figure 3A; Figure 3C shows a balanced circuit model that shows when the signal speed Beyond a certain range, it is possible to introduce these artifacts into the signal passing through the circuit; Figure 3D shows an exemplary layout, in which one M0SFET element uses nine standard M0SFET modules to make larger M0SFET (actually amplified gate) so that the EEG of the M0SFET element is nine times larger than that of a general M0SFET module; Figure 4 shows a typical circuit using a number of differential amplifiers divided by 2 dividers Architecture; Figure 5A shows the design flow or steps of these differential amplifiers or circuits that can be used in the circuit architecture of Figure 4; Figure 5B shows the gate determined by an EEG (a function of width W and length L) Illustrative transistor layout in the pole region. 23 200412026 Figure 5C shows an exemplary perspective view of a resistor layout; Figure 5D shows an exemplary layout of an interactive winding transformer; Figure 6 shows that Figure 4 contains an inductor Figure 7A shows a symbol or mark, which includes a differential amplifier designed according to the present invention and can be used as a building block; and Figure 7B shows four above-mentioned building blocks, which are continuously connected To reduce the signal frequency divided by 16. [Simplified description of component representative symbols] 102 Receiver 103 Optical-electrical converter 104 Transmitter 106 Conversion resistance amplifier 108 Radiation limiting amplifier 110 Clock & material reply (CDR) 114 Driver 116 Other circuit 130 Transmitter 133 Antenna 1 3 6 Low Noise Amplifier 138 Mixer 135 Oscillator 144 Power Amplifier 142 Upconverter 24 2004 12026 140 Modulator 200 Differential Circuit 202 Differential Amplifier 204 Differential Amplifier 206 Differential Amplifier 208 Current Source 302 Model 310 Balance Circuit module 320 Exemplary layout 322 MOSFET device 400 Exemplary circuit 520 Exemplary transistor layout 522 Gate area 530 Exemplary resistance 540 Transformer 542 Strip 544 Strip 600 Circuit 702, 718 input 704, 720 input 706, 722 output 708, 724 output 25