TW200411896A - ESD protection device - Google Patents

Abstract

An electrostatic discharge (ESD) protection device is composed of Zener diode. The ESD protection device has a Zener diode positioned in a substrate of a semiconductor wafer, a dielectric layer positioned on the substrate, a pad metal positioned on a surface of the dielectric layer above the Zener diode, at least a first contact plug positioned in the dielectric layer and electrically connecting the pad metal and the Zener diode, a passivation layer covering a surface of the semiconductor wafer and exposing a portion of a surface of the pad metal, at least a doped region positioned in the substrate and beyond the Zener diode, at least a power line positioned on the dielectric layer of the semiconductor wafer, and at least a second contact plug electrically connecting the doped region and the power line.

Description

200411896 V. Description of the invention α) Technical field to which the invention belongs The present invention provides an ESD protection circuit element composed of a Zener diode (Zener diode :), especially a combination of a pad and a Kina diode ESD protection circuit components. The prior art (; electrostatic discharge (ESD) phenomenon is a common phenomenon in semiconductor manufacturing processes, and the excessive charge brought by it will pass through the I / O pins of the integrated circuit in a very short time ( pin) into the integrated circuit and destroy the internal circuit of the integrated circuit (internai circuit). In order to solve this problem, manufacturers usually set a protection circuit between the internal circuit and the I / 0 pin, the protection circuit must Start before the pulse of electrostatic discharge (pulse) reaches the internal circuit, in order to quickly eliminate the excessive voltage, thereby reducing the damage caused by the ESD phenomenon. Known methods to avoid electrostatic breakdown caused by electrostatic pulses are Use a _well-p-type substrate (n we 1 hp substrate diode) or a metal oxide semiconductor field effect transistor (MOSFET) parasitic diode as the ESD protection circuit element. Please Refer to FIG. 1. FIG. 1 is a schematic structural diagram of a conventional MOS diode as an ESD protection circuit element. The metal oxygen The semiconductor diode system is formed on a p-type substrate i.

200411896

The top layer of the upper P-type substrate 10 is formed with a gambling region, and includes a P-type source 12 and a P-type drain 14. Yishanxi 2 " On / 1-. A gate conductive layer and a gate oxide layer 18 made of polycrystal 1 ine silicon, and located on the surface of the N-type well 11 area / η; and Between the drains 1 and 4, it constitutes a PM0S transistor / a high-conversion f㉟1 2 η failure region (n + pickup region) 2 0 is adjacent to the p-type source and the collection region 2 0 and P-type A source mound is formed on the source electrode 12: 2 electrode C common source e1ectrode) 22 ° Oppositely, a p-type well 31 region is formed on the surface of the other end of the P-type substrate 10, and the p-type well 31 contains There is an N-type source 32 and an n-type drain 34. A gate conductive layer 36 made of polycrystalline silicon (polycrystalline silicon) is formed on a gate oxide layer 38, and is located on the surface of the p-type well 31 in the area of the source 32 and the drain. Between the poles 34, an NMOS transistor is thus formed. A p + pickup region 40 with a rain-to-contamination concentration is adjacent to the N-type source 32, and a common source electrode is formed on the p-collection region 40 and the N-type source 32. ) 42. An electrode 44 is in contact with both the PS drain 14 of the PMOS and the N-type drain 34 of the NMOS, and is connected to the input (inpUt) and output (output) terminals of the circuit. Among them, the p-type well 31 area in the p-type substrate 10 and the N-type drain 34 system constitute a P-type well-N drain diode 45, and the N-type well 11 The region and the p-type drain 丨 4 form an N-well-p drain diode 46. Diodes 45 and 46 form an ESD protection circuit element to avoid electrostatic pulses from the input and output terminals

Page 7 200411896 V. Description of the invention (3) (electrostatic pulses) cause electrostatic breakdown. However, because the diodes 4, 5, and 6 have high internal resistance, a larger diode area is required to fully accept the input and output of the circuit (1 / 0) Electrostatic pulses. Therefore, the conventional technology not only needs to use a complicated copying process to make the above-mentioned complex diode ESD protection circuit element, but also the ESD protection circuit element will occupy a large layout area. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide an ESD protection circuit element composed of a kinah diode, and the kinah diode system is formed under a pad to solve the above-mentioned complicated process and excessive layout area. Caused by. In a preferred embodiment of the present invention, the ESD protection circuit element includes: a kina diode disposed in a substrate of a semiconductor wafer; a dielectric layer disposed on the substrate; and a pad metal ( pad metal) disposed on the surface of the dielectric layer above the kinah diode; at least one first contact plug is disposed in the dielectric layer and electrically connects the shield metal and the Gina diode; a protective layer covering the surface of the semiconductor wafer and exposing a part of the surface of the pad metal; at least one doped region

Page 8 ^: --- 200411896 V. Description of the invention (4) The domain is provided in a substrate other than the kinah diode; at least one power line is provided in the protective layer of the semiconductor wafer And at least one second contact plug for electrically connecting the doped region and the power line. Since the ESD protection circuit element provided by the present invention directly forms a quina diode under a single word, the earth metal oxide semiconductor diode (MOS diode) in the conventional technology can be saved on the wafer. The large area of the tool 1 can be formed by the reflector of the pad to simplify the semiconductor manufacturing process. Embodiments Please refer to FIGS. 2 to 5. FIGS. 2 to 5 are schematic diagrams of a method for manufacturing an ESD protection circuit element composed of a kine diode according to the present invention. As shown in FIG. 2, the ESD protection circuit element is formed on a P-type silicon substrate 61 of a half-conductor & wafer 60. According to the present invention, a dielectric layer 62 and a light and layer 64 are sequentially formed on the surface of the semiconductor wafer, and then a plurality of contact holes 65 are formed in the dielectric layer 62 by a yellow light and etching process. As shown in FIG. 3, after removing the first photoresist layer 64 on the surface of the semiconductor wafer 60, a first metal layer (not shown) is then deposited on the surface of the semiconductor wafer 60 to fill the contact holes 65, and a chemical is used. Mechanical grinding or back #

200411896 V. Description of the invention (5) 'Carving process' to form a plurality of contact plugs 66. A second metal layer is then deposited, and a yellow light and etching process is performed to form at least one corresponding pad metal 68 'over each contact plug 66 and then form a semiconductor wafer 60 surface. A passivation layer 70 covers the pad metal 68. Among them, the 'contact plug 66 and the pad metal 68 can also be formed by a dual damascene process to form 0. As shown in FIG. 4, a second photoresist layer 7 2 is formed on the surface of the semiconductor wafer 60. A yellow light and etching process is performed to define and form a guard opening (open) 73 in the compliance layer 70 above each guard metal 6 8. Subsequently, a first and a second ion implantation process are sequentially performed. The first ion implantation process is an N-type or p-type ion implantation process, and the second ion implantation process is a P-type or _ In the ion implantation process, a different cloth energy or different dopant weight is used to selectively form an N-type doped region on the substrate, and a p-type doped region is or a P-type dopant. The impurity region is above, and the N-type doped region is at the lower electrode body 74, as shown in FIG. Which Kina Diode? The quality change is about E13 ~ E14Cm-2, the dose of P dopant is about E13 ~ EUcmt. It is worth noting that the above-mentioned method of manufacturing an integrated ESD protection circuit element of the present invention is only Φ The first embodiment is described, that is, the first ion cloth implantation process or the Haide Jiazi sub-plantation implantation process can also be implemented in the deposition step or each step of the dielectric layer 62.

200411896 V. Invention description 6 Before the process of 5 ', even one of the ion implantation processes was performed first, and then after the pad opening 73 was formed, another ion implantation process was performed to form a substrate under the pad metal 68. Nano diode 74. Please refer to FIG. 6 'FIG. 6 is a schematic cross-sectional structure diagram of an ESD protection circuit element of the present invention. The ESD protection circuit element includes a kinah diode 74 formed on a P-type silicon substrate 61 of a semiconductor wafer 60. A pad metal 68 is formed above the kinah diode 74, and the pad metal 68 and A dielectric layer 62 is provided between the tomb diodes 7 and 4 to separate them, and a plurality of first contact plugs 6 are formed in the dielectric layer 62 to electrically connect the kinah diode 74 and the protective layer. The pad metal 68 is provided with an input / output (I / 〇) terminal (not shown) on the pad metal 68 to receive external positive and negative pulse waves. In addition, a protective layer 70 is provided above the guard metal 68 to protect all internal circuits of the semiconductor wafer 60, and a plurality of pad openings 73 are formed thereon to expose the pad metal 68. position. In addition, a plurality of P-type doped regions 5 i are formed in the broken substrate 61 adjacent to the kinah diode 74 and a plurality of contact plugs 76 are formed above each P-type doped region 75. The incoming call is connected to the power line (power 1i ne) 78 ° formed in the conductor chip 60 when a positive pulse is input from the pad metal 6 8 'The positive pulse will pass through the contact plugs 6 6 is passed to the kinah diode 74. At this time, for the kinah diode 74, its electrical performance is a two-diode bias region, and the characteristics of the kinah diode 74 are located in Reverse bias $

200411896 V. Description of the invention (7) The input voltage can be changed within a certain range without affecting a nearly fixed output voltage. When a negative pulse enters from the protection metal 6 _, the negative pulse will pass through the first contact plug 6 6 to the kinah diode 7 4. At this time, the kinah two For the polar body 74, its electrical performance is a forward biased region, and the kinah diode 74 has a barrier voltage in the forward biased region, and when the negative pulse wave ’s If the voltage does not reach the barrier's voltage, the forward current will approach zero, and the purpose of protecting the circuit is achieved. Among them, the negative pulse wave (negatiVe Pu 1 se) is grounded via the contact plug 76. On the contrary, when the ESD protection circuit element of the present invention is formed in an N-type silicon substrate or an N-type well, at this time, the doped region electrically connected to the contact plug 66 is an N-type doped region, and the aforementioned The operation is about the opposite. In addition. The E S D protection circuit element of the present invention can also directly ground the Shi Xi substrate to save the processes required for each of the N-type or P-type doped regions, contact plugs, and power lines. b Compared with the conventional technology, the ESD protection circuit element provided by the present invention: (1) forming a kina diode under a protective pad, so that the conventional technology can be saved. s diode) occupies a considerable amount of component space on the wafer, and the kinescope diode can be formed by using the mask of the pad as a reflector, so that it can save the complicated copying process.

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Page 13 200411896 Simple illustration of the diagram Simple illustration of the diagram Figure 1 shows the structure of a conventional metal oxide semiconductor diode (MOS diode). FIG. 2 to FIG. 5 are schematic diagrams of a method for fabricating an ESD protection circuit element using a kinad diode according to the present invention. FIG. 6 is a schematic cross-sectional structure diagram of an ESD protection circuit element of the present invention. Explanation of symbols in the figure 10 Base 11 N-well 12 '32 Source 14> 34 Drain 16 ^ 36 Gate conductive layer 18 ^ 38 Gate oxide 20 η failure region 31 P-well 40 ρ failure region 42 Source electrode 44 > and electrode 45 '46 Diode 60 semiconductor wafer 61 silicon substrate 62 dielectric layer 64 first photoresist layer 65 contact hole 66 first contact plug 68 pad metal 70 protective layer 72 second Photoresist layer 73 Protective pad opening 74 Kina diode 75 Doped region 76 Second contact plug 78 Power line

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Claims (1)

200411896 6. Scope of patent application ~ ESD protection circuit elements, including ESD protection circuit elements, which are located in the substrate of a semiconductor wafer; a dielectric layer, which is provided on the substrate; pad metal), which is disposed on the surface of the dielectric layer above the Kina diode; ^ at least one first plug, a contact plug, provided in the dielectric 9 'and electrically connected to the pad A metal and the quina diode; and, a protective layer covering the surface of the semiconductor wafer and exposing a part of the surface of the shield metal. 2 # · If the ESD protection circuit element of the first patent application scope further includes a doped region, which is provided in a substrate other than the quina diode; ^ ~ a power line, which is provided in the semiconductor On the dielectric layer of the wafer; and ^ i-a second contact plug for electrically connecting the doped region and the electrical as described in the application, π ~-doped region quina diode system is doped by an N type It is constructed by stacking below the area. 4. If the ESD protection circuit element of item 3 of the patent application scope, wherein 200411896 6. Scope of patent application " B 一 ^ 'Substrate 1 is a P-type silicon substrate. 5 · If the ESD protection circuit element of item 3 of the patent application scope, the substrate in i is a P-well (P we 1 1). 6. The ESD protection circuit element according to item 1 of the patent application scope, wherein the quina diode system is composed of a P-type doped region and an N-type doped region stacked up and down. 'Among them 7. The substrate system of the ESD protection circuit element according to item 6 of the patent application scope is an N-type silicon substrate. 8. The ESD protection circuit element according to item 6 of the application, wherein the substrate is an N-well (N wel 1). 9. The ESD protection circuit element according to item 1 of the patent application scope, wherein the quina diode system is formed by stacking a P-type doped region and an N-type doped region, and the P-type doped region and the N-type The dopant doses of the doped regions are all about E13 ~ E14cnr2. 1 ·· An ESD protection circuit element, the ESD protection circuit element includes: a kinah diode disposed in a substrate of a semiconductor wafer; and a pad metal provided in the kinah Above the polar body and Page 16 200411896 VI. Scope of patent application Electrically connected to this kinade diode. 11 · If the ES protection circuit element of the 10th patent application scope further includes: a dielectric layer provided on the substrate; at least one first contact plug provided in the dielectric layer; Connecting the pad metal and the kinah polar body; and a protective layer covering the surface of the semiconductor wafer and exposing a part of the surface of the guard metal; wherein the substrate is in a grounded state to release the pad Electrostatic pulses to which metal is subjected. 12. If the ESW inactive circuit element in the nth item of the patent application scope further comprises: at least one doped region, provided in a substrate other than the quina diode; at least one power line, provided in On the dielectric layer of the semiconductor wafer; and a second contact plug is used to electrically connect the doped area and the electrical connector is used to discharge ^^^ the static resistance of the pad metal 13. Keener Page 17 200411896 Composed of lower stacks. 14. According to the patent application No. 13, the protection circuit element is a p-type silicon substrate. 15 · If the ES Teng protective circuit element of item 13 of the patent application scope, its base is a Pwell. -16 · If the ESW dwell circuit element of the scope of the patent application is No. 0, the quina diode system is composed of a P-type doped region and an N-type doped region. 17. The ESW circuit-protected circuit element according to item 16 of the application, wherein the present substrate is an N-type silicon substrate. Λ18. For example, the ESW unprotected circuit element in the patent application No. 16 and the substrate is an N-well. 19, such as the ESm dwell circuit element in the scope of the patent application No. 10, the quina diode system is composed of a P-type doped region and an N-type doped region, a stack% ^, and the P-type Both the doped region and the N-type doped region are about E13 ~ E14cnr2.