TW200410501A - Sigma-delta modulator - Google Patents

Abstract

A sigma-delta modulator. The sigma-delta modulator comprises an integrator, a first quantizer, a dither generator and an adding device. An input terminal of the first quantizer and an input terminal of the dither generator are coupled to an output terminal of the integrator. The first quantizer generates a first random signal. The dither generator comprises a second quantizer for generating a second random signal, an input terminal thereof coupling to the output of the integrator; a random sequencer for receiving the first random signal and the second random signal to produce a third random signal output; and an attenuator for attenuating the third random signal to produce a dither signal to output. The dither signal is added to an input terminal of the integrator by the adding device.

Description

200410501 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to an integral triangle modulator, in particular, three types of integral triangles including a high-frequency dither generator = a prior art t is an integral triangle (Sigma-delta) technology (as part of the digital-to-analog-to-digital conversion function) is widely used in devices such as phone calls, CD players, and so on. "And Tian Yin is Because this technology allows circuit variations to be implemented in integrated circuit II, 16-bit or more linear converters can be implemented in integrated circuits, such as flash converters, which are inexpensive.乂 Integral dihedral converter is not without its shortcomings because it needs to say ― rate processing, but technology that pulls low power (such as CM0s), etc. == rate, especially when processing broadband signals such as digital wireless signals 7 2 outside 7 2 The signal needs to be fed back, so the integral delta converter will be affected by weeks, '

Noise (spuri0us tone) is generated (in the frequency band or super loud. Although the conventional periodic noise and spurious tone modulation: I, for example, about 9 follows the full scale), when using the same H When the ministry does not have a practical role in the data acquisition system, noise and spurious tones will be unpleasant to the user. When the signal required by those who do not need it is small, the noise and tones are significant ° = periodic noise Noise and tones are often referred to as idle channel noise (丨 ^ 1 C 〇 channel noise) 〇 Known techniques used to eliminate periodic noise and tones are the traditional way of transmuting, 'whiten' periodicity Noise and sound * ^ Turn to M and say, so compressed

200410501 V. Description of the invention (2) " '1-^ ren' This technology includes adding a small high-frequency di ther signal (noise), ^ tones beyond the frequency band (such as 25KHz sine wave, higher than The frequency range that the human ear hears) turns into the integral delta converter. When periodic noise and spurious tones cannot be completely removed, it is not entirely beneficial to add high-frequency dithering signals, because high-frequency dithering is added. The signal will increase the noise of the converter output, and the addition of tones outside the frequency band will reduce the tones in the frequency band. Because the converter will process the required signals and the tones outside the frequency band under saturation, it will affect the dynamics of the converter. range.

Steven R. Norsworthy in U.S. Patent No. 45,144,308, filed on September 1, 1992, "Idle Channel Tone and Periodic Noise Suppression for Sigma-Delta Modulators Using High-Level Dither" proposed a method of using digital to generate high-frequency dithering signals. The mechanism 'improves the performance of the integral delta modulator by reducing the periodic noise and spurious tones in the output signal of the modulator, but the addition of high frequency dithering signals to improve the performance of the integral delta modulator also Will reduce the dynamic range of the integral delta modulator, so a technique that uses high frequency dithering to improve the performance of the integral delta modulator without reducing the dynamic range of the integral delta modulator is needed.

No. rs worthy et al., US Patent No. 5,745,061, filed July 28, 1995 nMethod of Improving the Stability of a Sigma-Delta Modulator Employing Dither · 1 proposes a method for improving the integration triangle using high frequency dithering The performance of the modulator does not reduce the dynamic range of the integral delta modulator. However, in this technology, a random random number generator is required. This mechanism is also better than using the patent No. 5, 1 44, 3 08

, 0 ^ -8265TWF (nl); P2OO2-O23; ELLEN.ptd Page 7 200410501 V. The method in the description of the invention (3) is much more complicated, so using this mechanism requires more expensive hardware costs, so it needs a kind of high utilization Frequency dithering technique to reduce idle channel tones without the need for expensive hardware costs. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide an integral delta modulator, which can reduce the idle channel tone without reducing the dynamic range of the integral delta modulator. Another object of the present invention is to provide an integrating delta modulator, which has a simpler mechanism than the conventional technology, thereby greatly reducing the frequency jitter designed and manufactured to achieve the upper divider and a quantized divider. The product and the second minus the third will be outside the south frequency. The localizer and the unit sequencer include the product. The first device is connected to the product. The random number of the signal is stated. The sender of the present invention, the high-frequency tremor generator, and the addition dream ==: the input end of the generator are all light generator packages; the first = 随机 a random signal state is used to generate a second random signal At the output end of the reduced wheel, the random number sequencer uses ::: 's wheel random signal to generate a high-frequency dithering signal. Wheel f subtracter ί :: is sent to the input of the integrator. : Rainbow β gives out another kind of high-frequency dither generator, Doudou & Ranshi, 'Unit quantizer: the input terminal of the two-unit unit is coupled to the integral two random implementation logic & The output end of the digital logic circuit

200410501 Five invention description (4) No. to receive the first random input signal and the second random signal to generate a high-frequency round-end end. Earth-neck tremor signal comparator, random chaos iinn; high-frequency tremor generator, which includes, the device is used to generate the first: random letter: number = converter and attenuator, split-wheel output, random number sequence = car The input terminal of the benefit is coupled to the random number sequencer to receive the first and third digital logic signals to generate a third random signal output. The unit is' / ^ and the second random signal, and 旎 is converted into an analog signal wheel.锝: The second will generate the second high-frequency dither signal and add it; = = ”The analog signal is input to the input of the integrator. The device is used to send the high-frequency dither signal in order to make the present invention significantly easier. Understand that the following special κ — other purposes, features, and advantages can be explained in more detail, such as the following examples ^ Examples, and in conjunction with the accompanying diagrams, the implementation of the diagram is not a score of the present invention ^ one example points Triangle modulator's stage Γδ〇 '/, is a 2 ^ modulator b converter has a signal input stage 140 and a signal input angle, wailing' integral triangle modulator in the second example is the second-order integral 3 1 = Γ / There is an integrator ▲ between the input stage 140 and the quantizer 116, and the product The number of integrator in the dichotomous modulator determines the order of the integral diagonal modulator. The integral delta modulator includes the feedforward path, fedback path, and The second feedback path, the third feedback path, and the fourth feedback path. The pre-feedback path includes the first gainer in order.

〇m-8265TWF (η 1); Ρ2002-023; ELLEN. P t d

200410501 V. Description of the invention (5) 102, the first adder 104, the second adder 106, the first integrator 108, the first gainer 110, the third adder U2, the second integrator 114 二 和 Quantizer 11 6. The first feedback path is from the signal output stage 5o through the first inverting gainer 118 to the third adder 112. The second feedback path is from the signal output stage 150 through the high-frequency dither generator 315 to the second adder 006. The third feedback path is from the signal output stage 1 50 to the first adder 104 via the second inverting gainer 2 2 0. The fourth feedback path is passed by the output of the first integrator 108

Jl moves the generator 130 to the second adder 106. In addition, the first gainer 10 has a first gain coefficient (not shown in the first figure), the second gainer 丨 丨 has a second gain coefficient (not shown in the first figure), and the first inverse The phase gain device ii 8 has a second gain factor (not shown in the figure), the second inverting gain device 120 has a fourth gain factor (not shown in the figure J), and the first gain coefficient, the The absolute values of the second gain coefficient, the third gain coefficient, and the fourth gain coefficient are all less than 1. The high-frequency jitter generator 13 includes a second quantizer 136, a random sequencer 134, and an attenuator 132. The input of the second quantizer 136 is coupled to the output of the first integrator 108, and the second quantizer 136 Generate a second random signal s and send the second random signal 3 ^ to the random number sequencer 34. The quantizer 6 generates the first random signal SR1 and sends the first random signal to the random number sequencer 134 via the second feedback path. The random number sequencer 134 is a 1-bit logic circuit that implements XOR logic. The random number sequencer 34 receives a first random signal and a second random signal SR2 to generate a third random signal 'and generates a third random signal. The signal s is input to the attenuator 132. The attenuator 132 attenuates the third random signal & with high frequency dithering 彳 § No. 8 (1) and inputs the second frequency adder 106 to the frequency dithering signal center.

200410501 V. Description of the invention (6) In the first figure, two are described. The scope of the present invention is not limited to the embodiment of the white and two-diagonal modulator, but the triangular modulator. The present invention can also be used for products of other orders. Fig. 2 shows a second schematic diagram of the present invention. In this embodiment, the analog conversion of the integral delta modulator of column w is provided. The delta converter has a cost-effective, sub-delta modulator to implement a digital input stage 240 for receiving digital signals. The output stage is 250, and the signal angle modulator is a second-order product / three Yt '. The integral three-bit quantizer 216 in this embodiment has a product ^ ^ number input stage 24 0 and a single m ^ Λι. Eight product knives 208 and 214 ', and the number of points r: The number of angler fish determines the order of the number of points of the triangle modulator @ 一 一刀 二 角 角 器 includes feedforward path, first feedback path (Feedback path), second feedback path, third) feedback path H and fourth feedback path. The predecessor path includes the first-gain device __, /, and, in order. The addition state 204, the second adder 206, the first integrator 208, the brother state, the surplus state 210, the third adder 212, the second integrator 214, and the unit integrator 216. The first feedback path is from the signal output stage 25 to the third adder 212 through the first inverting gainer 218, and the signal input from the first inverting gainer 2 18 to the third adder 21 2 has n bits. The second feedback path is from the signal output stage 2 50 to the second adder 206 through the high-frequency dither generator 2 3 0. The third feedback path is from the signal output stage 2 50 to the first adder 2 0 4 through the second inverting gainer 2 2 0, and the signal input to the first adder 204 by the second inverting gainer 2 2 0 has n bits. The fourth feedback path is from the output of the first integrator 208 to the second adder 206 via the high-frequency dither generator 230. In addition, the first gainer 202 has a first gain coefficient (not shown in the first

069Ϊ-8265TWF (η1); P2002-023; ELLEN.ptd Page 11 200410501 V. Description of the invention (is ------ 1 > Figure ^,), the second gainer 210 has a second benefit coefficient (not It is shown in the 2nd LL that the inverting gainer 218 has a third gain coefficient (not shown in the figure = 2), and the second inverting gainer 22 has a fourth gain coefficient (not shown in the figure 2), And the absolute values of the first gain coefficient, the second gain coefficient, the third gain coefficient, and the fourth gain coefficient are all less than 1. The π-frequency jitter is generated as 23, which includes the second unit quantizer 236 and logic, path 234, and second. The input terminal of the unit cell quantizer 236 is coupled to the round-out end of the first integral w 2 0 8 'The second unit cell quantizer 2 3 6 generates a second random signal core and sends the second random signal & to the logic circuit. 234. The unit element quantizer 216 generates a first random signal core and sends the first random seventh number SR1 to the logic circuit 234 via the second feedback path. The logic circuit 234 is to implement x〇R logic 1 number = logic circuit, logic circuit 234 Multiplies the first random signal and the second P pass machine 号 5 ^ to generate a third random The value of the signal SR3 and the third random signal SRS is a 1-bit logic output. In an integral delta modulator that realizes digital analog conversion, the third random signal Sr3 is a high-frequency dither signal Sd, so the 'logic circuit 23 4 directly The third random signal Sr3 is input to the second adder 206. The second embodiment of the second-order integral delta modulator is illustrated in FIG. 2. However, the scope of the present invention is not limited to this, and the present invention can also be applied to other stages. Figure 3 shows the schematic diagram of the structure of the integral delta modulator of the third embodiment of the present invention. The integral delta modulator in this embodiment is used to implement analog-to-digital conversion and has a signal input stage 34. 0 and signal output stage 350, signal input stage 3 4 0 receive analog bit signal input, integral in this embodiment

^ r8265TWF (nl); P2002-023; ELLEN.ptd Page 12 200410501 V. Description of the invention (8) The triangular modulator is a second-order integral triangular modulator. There are integrators 308 and 314 in between, and the number of integrators in the integral delta modulator determines the order of the integral delta modulator. The integral triangle modulator includes a feed path, a first feedback path, a second feedback path, a third feedback path, and a fourth feedback path. The feed forward path includes a first gainer 302, a first adder 304, a second adder 306, a first integrator 308, a second gainer 310, a third adder 312, and a second The integrator 314 and the unit quantizer 316. The first feedback path is from the signal output stage 35o through the first unit-bit digital-to-analog converter 3 4 2 and the first inverting gain converter 3 丨 8 to the third adder 3 1 2. The second feedback path is from the signal output stage 3 50 to the high-frequency dither generator 3 3 0 to the brother 1 adder 3 6. The third feedback path is from the signal output stage 350 to the first adder 304 via the first unit-bit digital-to-analog converter 342 and the second inverting gainer 320. The fourth feedback path is from the output of the first integrator 308 to the second adder 306 via the high-frequency dither generator 330. In addition, the first gainer 3 02 has a first gain coefficient (not shown in FIG. 3), the second gainer 3 10 has a second gain coefficient (not shown in FIG. 3), and the first inverting gain The converter 318 has a third gain coefficient (not shown in the third figure), the second inverting gain device 320 has a fourth gain coefficient (not shown in the third figure), and the first gain coefficient, the second gain coefficient, Both the third and fourth gain coefficients have absolute values less than one. The local frequency generating motion 330 includes a comparison of 3 3 6, a logic circuit 3 3 4, a second unit-bit digital-to-analog converter 344, and a third inverting gain amplifier 3 32. The input of the comparator 33 6 is coupled to the first Output of an integrator 308, comparator

Q6ft7: f8265TWF (nl); P2002-023; ELLEN.ptd Page 13 '^ 200410501 V. Description of the invention (9) 336 generates a second random signal Sr2 and sends the second random signal Sr2 to the logic circuit 334. The unit cell quantizer 3116 generates the first random signal SR1 and sends the first random signal Sri to the logic circuit 3 34 via the second feedback path. The logic circuit 334 is a digital logic circuit implementing xOR logic. The logic circuit 334 receives the first random signal SR1 and the second random signal SR2 to generate a third random signal sRS and outputs the third random signal Sr3. The third random signal Sr3 is converted into an analog signal by the second unit digital analog converter 344, and the third inverting gain unit 332 attenuates the third random signal Sr3 to generate a high-frequency dither signal Sd and inputs the high-frequency dither signal Sd to the second Adder 3 0 6. The third inverting gain unit 332 has a fifth gain coefficient (not shown in FIG. 3), and the absolute value of the fifth gain coefficient is greater than the first gain coefficient, the second gain coefficient, the third gain coefficient, and the fourth gain. The absolute value of the coefficient is much smaller. 0. An embodiment of the second-order integral triangular modulator is illustrated in FIG. 3, but the scope of the present invention is not limited to this, and the present invention can also be used for integral triangular modulators of other orders. Figures 4a and 4b show the frequency response of the output signal after the integral delta modulator with the input signal of zero to the DC signal with zero input value, and the Γ is connected to t4c! And Figure 4d shows the DC signal with zero input value. Frequency response diagram of the output signal after the signal reaches the product / knife diagonal modulator of the present invention. As shown in the figure, the X-axis represents the frequency. The unit is Hertz (Hz). The γ-axis is the signal strength I and the unit is decibel (dB). Between the frequencies & ^ " in Figures 4a and 4c, Frequencies are enclosed in Figures 4b and 4d. ~ 16〇 In Figures 4a and ㈣, you can see that between === overhang, there is obvious idleness in the ^ half domain

200410501 V. Explanation of the invention (ίο) ---, channel = (idle channel tone) ′ In the & diagram and the rule, it can be found that the use of the borrower II & of the present invention will be eliminated. The product knife two-corner modulator ‘Idle channel tone Yes’ indicates the integral triangle modulation response diagram of a DC signal with an input value of 0.003 to a motion signal. Figure 5c and 篦 rhui have recognized the frequency response diagram of the DC signal ffl m-, Y 4L ^ * of the K-state rear wheel output signal with an integrated triangular value of 0.03. Such as degrees, the unit is Babe 2, the unit is Hertz (HZ), and the Y-axis is the signal strength. T16QQkHzW 'The frequency range in Figures 5a and 5c is ~ 2: Figures 5b and 5d The range of the intermediate frequency is between UZ (J k Η z 'in the first Qizhigema ~ there is a clear idle channel tone \ ΛΛ, it can be seen that the fifth of the present invention is now used in the frequency domain. Figure and 5d In the picture, it can be removed. W The corner of the knife will fade, and the tone of the idle channel will be cancelled. Figure 6a and Figure 6b. ΞίLi is zero to the X-axis of the present invention representing the frequency, single: the second is the wheel frequency, the response diagram. As shown in the figure 'decibel (dB), the force flute R is the Hertz (), the Y-axis is the signal strength The unit is between the fihm I graph and the graph. The frequency range in the graph is 0 ~ 16 00kHz ^ The frequency range of the Mfih graph and the graph in 6d is between 0 ~ 20kHz, the AH is the same as the if number The average value of the noise-to-noise ratio (SNR) is 49.27dB, while in # 1-, the average value of the signal-to-noise ratio is 49.05dB. Noise ratio, and using no dithering

200410501 V. Description of the invention (11) ----- The integral triangle modulation of the signal The signal-to-noise ratio of the signal almost proves that the use of the integral triangle modulator of the present invention will not be the same, so it can be described above. 4 of the present invention, flood-to-clutter ratio. It can reduce the idle range without reducing the dynamic range of the integral delta modulator 2: the angular modulator, its channel tone, and its simple know-how. The present invention reduces the design and production costs. 1, so it can be achieved as above, but it is not used without departing from the spirit of the invention, so the protector of the invention shall prevail.

Although the present invention has been disclosed with a preferred embodiment to limit the present invention, anyone skilled in the art can make some modifications and retouching within the scope and scope, as defined by the appended patent scope.

200410501 Brief Description of Drawings Figure 1 shows the structure of the integral delta modulator of the first embodiment of the present invention. Fig. 2 is a schematic diagram showing the structure of an integrating delta modulator according to a second embodiment of the present invention. Fig. 3 shows the structure of an integrating delta modulator according to a third embodiment of the present invention. Figures 4a and 4b show the frequency response of the output signal from a DC signal with an input value of zero to an integrating delta modulator without any high-frequency dithering signals. Figures 4c and 4d show the frequency response of the output signal after the DC signal with an input value of zero reaches the integrating delta modulator of the present invention. Figures 5a and 5b show the frequency response of the output signal after a DC signal with an input value of 0.03 to an integrated delta modulator without any high-frequency dithering signal. Figures 5c and 5d show the frequency response diagrams of the output signals after the DC signal with an input value of 0.03 is applied to the integral delta modulator of the present invention. Figures 6a and 6b show the frequency response of the output signal after an AC signal with an input value of 0.03 to an integrated delta modulator without any high-frequency dithering signal. Figures 6c and 6d show the frequency response diagrams of the output signal after the AC signal having an input value of 0.03 is applied to the integral delta modulator of the present invention. Symbol description: 140, 24 0, 34 0 ~ signal input stage; 150, 250, 350 ~ signal output stage;

mi- 8265TWF (η 1); Ρ2002-023; ELLEN. pt d p. 17

U JU 200410501 The diagram briefly explains 102, 202, 302 ~ the first gainer; 1 0 4, 2 0 4, 3 0 4 ~ the first adder; I 0 6, 2 0 6, 3 0 6 ~ the second adder 108, 208, 308 to the first integrator; II 0, 2 1 0, 3 1 0 to the second gainer; 11 2, 2 1 2, 3 1 2 to the third adder; 114, 214, 314 ~ 2nd integrator; 11 6 ~ quantizer; 118, 218, 318 ~ first inverting gain unit 120, 220, 320 ~ second inverting gain unit 130, 230, 330 ~ high frequency dither generator 1 3 2 ~ Attenuator; 134 ~ Random number sequencer; 1 3 6 ~ Second quantizer; 2 1 6, 3 1 6 ~ Unit quantizer; 234, 33 4 ~ Logic circuit;

23 6 / ~ second unit quantization 32: · ασ, 33 2, ~ ~ third inverting gainer 33 6, ~ comparator; 34 2, ~ first unit digital analog converter 344, ~ second unit Digital analog converter Q ~ ° R1 first --- random signal Q ~ ° R2 'second random signal Q ~ ° R3, JL random signal and

Qm-m5TW (η 1); P2002-023; ELLEN. P t d p.18 200410501 The diagram briefly explains sd ~ high frequency dither signal. 1ϋ · ϋΙ ^ -8265TWF (nl); P2002-023; ELLEN.ptd page 19

Claims (1)

200410501 6. Scope of patent application 1. An integrating delta modulator, comprising: an integrator having an input end and an output end; a first quantizer for generating a first random signal having an input end The input terminal is coupled to the output terminal of the integrator; a high-frequency dither generator has an input terminal, the input terminal is coupled to the output terminal of the integrator, and includes: a second quantizer for To generate a second random signal, which has an input terminal coupled to the output of the integrator; a random number sequencer for receiving the first random signal and the second random signal to generate A third random signal output; and an attenuator for attenuating the third random signal to generate a high-frequency dither signal output; and an adding device for sending the high-frequency dither signal to the input of the integrator . 2. The integral delta modulator as described in item 1 of the patent application scope, wherein the second quantizer is a unitary quantizer. 3. The integrating delta modulator according to item 1 of the scope of patent application, wherein the second quantizer is a comparator. 4. The integral delta modulator as described in item 1 of the scope of patent application, wherein the random number sequencer is a digital logic circuit that implements X0R logic. 5. The integral delta modulator as described in item 1 of the scope of patent application, wherein the adding device is an adder. 6. A kind of integral delta modulator, including: an integrator with an input terminal and an output terminal; fer 8265TWF (η1); P2002-023; ELLEN.ptd Page 20 200410501 Sixth, the scope of the patent application-a first unit quantizer for generating a first random signal, which has an input terminal, the input terminal is coupled Connected to the output of the integrator; a high-frequency dither generator having an input, the input is coupled to the output of the integrator, and includes: a second unit quantizer for generating a The second random signal has an input terminal coupled to the output terminal of the integrator; and a random number sequencer for receiving the first random signal and the second random signal to generate a first random signal. Three random signal outputs; and an adding device for sending the high-frequency dither signal to the input of the integrator. 7. The integral delta modulator as described in item 6 of the scope of patent application, wherein the random number sequencer is a digital logic circuit that implements X0R logic. 8. The integral delta modulator as described in item 6 of the scope of patent application, wherein the adding device is an adder. 9. An integrating delta modulator, comprising: an integrator having an input end and an output end; a single-element quantizer for generating a first random signal having an input end coupled to the input end To the output of the integrator; a high-frequency dither generator having an input, the input is coupled to the output of the integrator and includes: a comparator for generating a second random signal, It has an input terminal, which is coupled to the output terminal of the integrator; a random sequencer is used to receive the first random signal and the first random signal -8265TWF (η 1); P2002-023; ELLEN. Pt d page 21 200410501 6. Patent application scope 2 Random signal to generate a third random signal output; a single-bit digital analog converter for converting the third The random signal is converted into an analog signal; and an attenuator for attenuating the analog signal to generate a high-frequency dithering signal output; and an adding device for sending the high-frequency dithering signal to the input of the integrator. 10. The integral delta modulator as described in item 9 of the scope of patent application, wherein the random number sequencer is a digital logic circuit that implements X0R logic. 11. The integral delta modulator according to item 9 of the scope of patent application, wherein the adding device is an adder. 1 2. The integral delta modulator as described in item 9 of the scope of patent application, wherein the attenuator is a gain device, and the gain device has a small gain factor of 0. -Μψ-8265TWF (η 1); P2002-023; ELLEN.ptd page 22