TW200409366A - Method of fabricating low temperature polysilicon thin film transistor - Google Patents

Abstract

A method of fabricating low temperature polysilicon thin film transistors is disclosed. First, two polysilicon islands are formed in a first region and a second region on a substrate. A gate insulating layer and a gate are formed on each polysilicon island respectively. A first ion implantation process is performed to form light doped drains surrounding the both gates. A second ion implantation process is followed to form a source and a drain surrounding the gate in the first region to form a first conductive type thin film transistor. A protective layer is formed selectively on the top surface and the sidewall of the both gates. A third ion implantation process is then performed to form a source and a drain surrounding the gate in the second region to form a second conductive type thin film transistor with light doped drains.

Description

200409366 V. Description of the invention (1) Technical field of the invention The present invention provides a method for manufacturing a low-temperature polycrystalline silicon thin film transistor, and more particularly, a method for manufacturing a PM0S and an NM0S thin film transistor at the same time. With the advancement of technology, light, thin, power-saving, and portable smart information products have flooded our living space, and displays have played a very important role in it, whether it is a mobile phone, personal digital assistant or It is a notebook computer, and all need a display as an interface for human-computer communication. However, the a-Si TFT LCD (a_Si TFT LCD), which has been heavily produced today, has been difficult to meet the requirements of lightness, power saving, and high quality due to the limitation of carrier mobility. It will be a low temperature polysilicon (LTPS) thin film liquid crystal display. Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a low temperature polycrystalline silicon thin film transistor liquid crystal display (LTPS TFT-LCD) 10. As shown in FIG. 1, the low-temperature polycrystalline silicon thin film liquid crystal display 10 mainly includes a substrate 12, and a pixel array region 14, a scanning line driving circuit region 16, and a data line driving circuit region 18 are provided on the substrate 12. . The pixel array area 14 is further provided with a plurality of parallel scanning lines 2 2 and a plurality of parallel scanning lines 22 and parallel to each other and perpendicular to each scanning.

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V. Description of the invention (2) The data line 2 4 of line 2 2 'and each scanning line 22 and each data line 2 define a pixel 26, and each pixel 26 includes a thin film The transistor 28 and a storage capacitor 30. Generally speaking, the thin film transistors 2 and 8 used in the pixel array region 14 are mostly NMOS thin film transistors with better electrical performance, and the scanning line driving region 16 and the data line driving region 18 each include a plurality of numbers. LTPS CMOS TFT (not shown), used as a logic circuit element to integrate a standard driver integrated circuit (IC) on a liquid crystal display panel, and further reduce production costs and module Processing time. /

The method of manufacturing a low temperature polycrystalline silicon thin film transistor in the conventional technology is described below by taking only two methods of simultaneously manufacturing a PM0s and an NMOS thin film transistor as examples'. Reference is made to FIGS. 2 to 7, which are schematic diagrams of a conventional method for fabricating a low-temperature polycrystalline silicon thin film transistor with a top gate structure. As shown in FIG. 2, the conventional low-temperature polycrystalline silicon thin film transistor system is fabricated on the substrate 12, and the surface of the substrate 12 includes a first region 40 and a first region 50 to form a PM, respectively. 〇s thin film transistor and φ at 1 NM at day ^ "^

A conventional method is to first form a buffer layer 32 on the substrate 12 to prevent the impurities in the substrate 12 from diffusing upward in subsequent processes to affect the shape of the thin film transistor, and then shape the surface of the buffer layer 32. An amorphous silicon thin film (not shown), and then the amorphous silicon thin film is melted and recrystallized into polycrystalline silicon thin film (not shown) by _ excimer laser recrystallization

200409366 V. Description of the invention (3) Subsequently, the formed polycrystalline silicon thin film was patterned by a yellow light and etching process to form a polysilicon island in the first region 40 and the second region 50 respectively. 34o As shown in FIG. 3, a chemical vapor deposition process or a thermal oxidation process is then performed to form a gate insulating layer 36 on the buffer layer 32 and cover the two polycrystalline stones. Island 3 4 above. Subsequently, a conductive layer is formed on the gate insulating layer 36, and a yellow light and etching process is performed to pattern the conductive layer to form a first gate in the first region 40 and the second region 50, respectively. Pole 3 8 and a second gate electrode 4 2. Then, as shown in FIG. 4, a first N-type ion distribution process is performed, and the first gate 38 and the second gate 42 are used as a screen, so that the first gate 38 and the second gate 4 A lightly doped drain electrode 4 4 is formed in the surrounding polycrystalline silicon island 3 4. As shown in FIG. 5, a first photoresist layer 45 is formed next to cover the second region 50 ′, and then a P-type ion distribution process is performed on the first region 40 to place the first gate electrode 38 on both sides. Two P-type doped regions are formed in the polycrystalline silicon island 34 as a first source electrode 46 and a first non-electrode electrode 48. Among them, the first source electrode 46, the first non-electrode electrode 48, and the first gate electrode 38 will form a PMOS transistor 60 together. After the first photoresist layer 45 is removed, a patterned second photoresist layer 51 is then formed as shown in FIG. 6 so as to form a second source or drain electrode in the second area 50. A hole 5 2 is formed in the photoresist layer 51, and then an N-type ion distribution process is performed to implant N-type ions into the polycrystalline silicon island below through the hole 5 2

Page 8, 200409366, description of the invention (4) 'to form two N-type heavily doped regions, as a second source 5 4 and a second ^ 5 6, wherein the second source 5 4 and the second drain 5 6 The second gate electrode 42 and the light 4 heterodrain electrode 44 will together form a NMOS transistor 70.

Then, as shown in FIG. 7, the second photoresist layer 51 is removed first, and then a dielectric two layer 58 is formed to cover the formed pM0s transistor 60 and NMOs transistor 70, which is inferior to the dielectric layer. A plurality of contact plugs 6 2 are formed in 5 8 to electrically connect the factory source 46, the first drain 48, the second source 54, and the second drain 56 respectively, and then the contact plugs 6 2 may be further processed. A further electrical connection process is used to electrically connect the formed NMOS transistor 70 and the pMOS transistor 60 to other circuit elements such as scan line 16, data line 18, storage capacitor 30 or pixel electrode.

Conventional techniques are used to make thin film transistors with lightly doped drain electrodes (such as the aforementioned NMOS transistors). Generally, a lower dose is used for the ion distribution value in the polycrystalline silicon islands on both sides of the gate. A lightly doped drain is formed, and then a patterned photoresist layer is used to cover a portion of the lightly doped heterodrain near the gate, and then a heavy dose ion distribution process is performed to form the source and the drain. As the line width of components becomes smaller and smaller, it is becoming more and more difficult to define the positions of lightly doped drains 4 and 4 using the yellow light process. It is easy to cause problems such as misalignment or inaccuracy, which affects low-temperature polycrystalline silicon. Electrical performance of thin film transistors. Therefore, how to improve the manufacturing method of low-temperature polycrystalline silicon thin film transistors is an important research topic at present. Summary of the Invention

200409366 V. Description of the invention (5) The main purpose of the present invention is to provide a method for manufacturing a low-temperature polycrystalline silicon thin film transistor. This method can define the position of a lightly doped drain by self-alignment to solve the conventional technology. Problem. A preferred embodiment of the present invention discloses a method for fabricating thin-film transistors of different conductivity types on a substrate. The surface of the substrate includes a first region and a second region, which are used to form a PMOS thin-film transistor and A NMOS film transistor. First, a polycrystalline silicon island is respectively formed on the first region and the second region of the substrate, and then a gate insulating layer is formed to cover each of the polycrystalline silicon island and the substrate, and then respectively in the first region and the second region. A first gate and a second gate are formed on the gate insulating layer, and then an N-type ion distribution process is performed first to each of the two sides of the first gate and the second gate. The polycrystalline silicon island forms a lightly doped drain electrode, and a P-type ion distribution process is performed on the first region to form a first source electrode and a first electrode in the polycrystalline silicon island around the first gate electrode. Then, a protective layer is selectively formed on the upper side and the side wall of the first gate and the second gate, and a third ion distribution process is performed to form the polysilicon islands around the second gate respectively. A second source and a second drain. The method for manufacturing a low-temperature polycrystalline silicon thin film transistor in the present invention uses a self-alignment method to define the position of a lightly doped drain electrode, so the problem of inaccurate alignment can be effectively improved. In addition, the invention also provides a method for manufacturing a low-temperature polycrystalline silicon thin film transistor with a composite gate, which can make the lightly doped drain

200409366 V. Description of the invention (6) The electrode is located under the composite gate to improve the electrical performance of the low-temperature polycrystalline silicon thin film electric crystal. Embodiments In a preferred embodiment of the present invention, a low temperature polysilicon complementary metal oxide semi conductor thin film transistor including a PMOS and a NMOS transistor is used as an example. The manufacturing method of the low temperature polycrystalline silicon thin film transistor of the present invention will be described. However, the application of the present invention is not limited to this, but can be applied to the display array area and scan line driving in a low temperature polycrystalline silicon thin film transistor liquid crystal display (LTPSTFT-LCD). Fabrication of PMOS and NMOS thin film transistors in various areas such as the circuit area and the data line drive circuit area. Please refer to FIGS. 8 to 13, which are schematic diagrams of a method for manufacturing a low-temperature polycrystalline silicon thin film transistor according to the present invention. As shown in FIG. 8, the low-temperature polycrystalline silicon complementary metal-oxide semiconductor thin film transistor system disclosed in this embodiment is fabricated on a substrate 112, and the surface of the substrate 112 includes a first region 120 and a second region 130. To form a PMOS film transistor and a NMOS film transistor, respectively. First, a buffer layer (1) 1 ^ {6]: 1376] :) 114 is formed on the substrate 1 1 2 to avoid impurities in the substrate 112 from diffusing upward in subsequent processes and affecting the quality of the formed thin film transistor. In the first region 1 2 0 and the second region 1 3 0 on the surface of the buffer layer 1 1 4, more than one are formed.

200409366 V. Description of the invention (7) Polysilicon island 116o Where polysilicon island 1 1 6 is manufactured, in addition to the process methods in the conventional techniques described above, a crystal grain boundary position can also be used. An excimer laser recrystallization process. This method first forms an amorphous silicon thin film (not shown) on the buffer layer 1 1 4. The amorphous silicon thin film is defined with at least one initiative to form a polycrystalline silicon island 1 16. Area, and then a mask layer is formed over the amorphous silicon film, and a first yellow light and I engraving process is performed to remove the mask layer in the active area, and then perform a calibration The molecular laser recrystallization process recrystallizes the amorphous silicon film in the first region 120 and the second region 130 into a polycrystalline silicon film, and then uses a second yellow light and money engraving process to remove the mask. Layer and the amorphous broken film, so that a polycrystalline silicon island 1 16 is formed in the first region 120 and the second region 130 respectively. As shown in FIG. 9, a chemical vapor deposition process is then performed to form a gate insulating layer (gateinsu 1 ating 1 ay er) 1 1 8 on the buffer layer 1 1 6 and cover the two polycrystalline silicon islands 1 1 6 on. Subsequently, a first conductive layer (not shown) is formed on the gate insulating layer 118, and a patterned first photoresist layer (not shown) is formed on the first conductive layer so that the first region and the A pattern of a first gate electrode 1 2 2 and a second gate electrode 1 2 4 is respectively defined in the second region, and an etching process is performed to separate the first region 1 2 0 and the second region 1 300 respectively. A first gate electrode 1 2 2 and a second gate electrode 1 2 4 are formed. After removing the first photoresist layer, a first N-type ion layout process is performed, using the first gate electrode 1 2 2 and the second gate electrode 1 2 4 as a mask, so that the first gate electrode 1 2 2

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A polysilicon island around the lightly doped gate and the second gate 1 2 4 is formed simultaneously in 1 1 6-126 ° shown by & ϊK ', and then a second photoresist layer 132 is formed to cover the first & field丄 30, and then perform a P-type ion distribution process on the first region 120. Since the distribution value of the two P-type ion-distribution processes far exceeds that of the first N-type ion-distribution process, a poly-P-type doped silicon will be formed on the polysilicon islands on both sides of the first gate 12 2. The miscellaneous region, as a first source electrode 1 34 and a first drain electrode 13 6, wherein the first source electrode 1 3 4, the first electrode 1 3 6 and the first gate electrode 1 2 2 together form a PM0S transistor. 140. As shown in FIG. 11, after the second photoresist layer 1 32 is removed, a self-alignment is selectively formed in the first region 120 and the second region 130. The protective layer 142 covers the upper surface and the sidewall of the first gate electrode 12 and the second gate electrode 12 respectively.

In a preferred embodiment of the present invention, the first gate electrode 12 and the second gate electrode 1 2 4 are both | lu (a 1) metal gate electrodes, and the protective layer 1 4 2 is electrically conductive by a second electrode. Layer, its manufacturing method is to form a precursor layer, such as gold (Au), on the surface of the substrate 1 1 2 and cover the gate insulating layer 1 1 8 and the first gate 1 2 2 and the second gate 1 2 4 and the predecessor layer will react with the metal gate to form a gold aluminum alloy to cover the first gate 1 2 2 and the second gate 1 2 4 The precursor layer on the upper surface and the side wall reacts to form a protective layer 1 42, and then the unreacted precursor layer is removed.

Page 13 200409366 V. Description of the invention (9) The surfaces of the first gate electrode 1 2 2 and the second gate electrode 1 2 4 form a self-aligning protection 厣 1 4 2. Among them, since the protective layer 1 4 2 is also composed of a conductive material, it will form a composite gate with the pre-formed brother gate 1 2 2 or the second gate 1 2 4 so that light doping The hybrid drain electrode 126 is located below the composite gate, which can effectively improve the electrical performance of the thin film transistor. In addition, the protective layer 1 4 2 formed by self-alignment can also be a non-conductive material, but the function of the protective layer 1 42 at this time is limited to being used as a lightly doped drain for the NM0s transistor i 50. Cover layer of poles 1 2 6. As shown in FIG. 12, a third photoresist layer 143 is then formed to cover the first region 120, and a second n-type ion distribution process is performed on the second region i 3 0 'using a compliance layer 1 4 2 is a cover layer, which protects the lightly doped electrode 1 2 6 below, and forms a two-type heavily doped region in the polycrystalline stone island 1 1 6 which is not covered with the protective layer 1 4 2 as A second source electrode 1 4 4 and a second drain electrode 1 4 6. Among them, a source 1 4 4, a 1 > and a pole 1 4 6, a second gate 1 2 4 and a lightly doped drain 126 will collectively form an NMOS transistor 150. Among them, the NMOS transistor 150 and the PM0S transistor 140 can be used to form a CMOS transistor as a logic circuit element. As shown in FIG. 13, the third photoresist layer 143 is then removed, and a dielectric layer 148 is formed to cover the formed PM0S transistor 140 and NMOS transistor 1 50 and the dielectric layer 1 4 A plurality of contact plugs 1 5 2 are formed in 8 to be electrically connected to the first source electrode 1 3 4, the first drain electrode 1 3 6, the second source electrode 1 4 4 and the second drain electrode 1 4 6 respectively. Further electrical connection to contact plugs 1 5 2

Page 14 200409366 V. Description of the Invention (Processing) The PM0S transistor 140 and NMOS transistor 150 are electrically connected to other circuit elements such as scan lines, data lines, storage capacitors or pixel electrodes. It is worth noting that although the above description is made of a PMOS transistor and an NMOS transistor including a lightly doped drain electrode, the method for manufacturing the low-temperature polycrystalline silicon thin film transistor of the present invention is described, but the present invention is not limited to this. Change the conductivity type of implanted ions to form a NMOS transistor and a PM0S transistor containing a lightly doped drain. Because of its manufacturing method, except for the conductivity type of the implanted ion, which is opposite to the previous embodiment, the remaining process steps They are all very similar. It should be easily understood by those skilled in the art according to the foregoing description, so it will not be repeated here. Compared with the conventional technology, the present invention uses a self-alignment process to selectively form a protective layer attached to the upper surface and side walls of each gate, and then uses the protective layer as a cover to perform subsequent source / drain It can accurately define the size and position of the lightly doped drain region in an NMOS or PM0S transistor, which effectively solves the problem of misalignment that is easy to occur in the conventional technology, thereby increasing the low temperature polycrystalline silicon thin film transistor process. Reliability. In addition, the present invention further discloses a method of using a second conductive layer as a protective layer to form a composite gate with the first conductive layer, and increasing the gate by the second conductive layer (5 layers). The area occupied by the electrode makes the previously formed lightly doped drain electrode be located below the composite gate, which will further accelerate the operation efficiency of the MOS transistor and improve the display products of the low temperature polycrystalline silicon thin film liquid crystal display.

Page 15 200409366 V. Description of the invention (11) Quality. The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 16 200409366 Brief description of the diagrams Brief description of the diagrams: Figures 1 to 7 are schematic diagrams of a conventional method for manufacturing a low-temperature polycrystalline silicon thin film transistor (LTPS TFT). FIG. 8 to FIG. 13 are schematic diagrams of a method for manufacturing a low temperature polycrystalline silicon thin film transistor (LTPS TFT) according to the present invention. Symbol description: 10 LTPS-TFT LCD 12 substrate 14 pixel array area 16 scanning line driving circuit 18 material line driving circuit 22 scanning line 24 data line 26 pixel 28 low temperature polycrystalline film transistor 30 storage capacitor 32 buffer layer 34 polysilicon island 36 gate insulating layer 38 first gate 40 first region 42 second gate 44 lightly doped drain 45 first photoresist layer 46 first source 48 first drain 50 second Area 51 Second photoresist layer 52 Hole 54 Second source 56 Second drain 58 Dielectric layer 60 PMOS transistor 62 Contact plug 70 NMOS transistor 112 Substrate

Page 17 200409366 Brief description of the diagram 114 Buffer layer 116 Polycrystalline silicon island 118 Gate insulating layer 120 First region 122 First inter electrode 124 Second gate 126 Lightly doped drain 130 Second region 132 Second photoresist layer 134 First source 136 First drain 140 PMOS transistor 142 Protective layer 143 Third photoresist layer 144 Second source 146 Second drain 148 Dielectric layer 150 NMOS transistor 152 Contact plug

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Claims (1)

200409366 VI. Application Patent Scope 1. A method for manufacturing a low temperature polysilicon thin film transistor (LTPS TFT), the method includes the following steps: providing a substrate, the surface of the substrate A first region and a second region are defined; a polysilicon island is respectively formed in the first region and the second region above the substrate; and a gate insulating layer is formed ) Covering the substrate and the polycrystalline silicon islands; forming a first conductive layer over the gate insulating layer; forming a patterned photoresist layer over the first conductive layer so that the first region and the A first gate and a second gate are defined in the second region, respectively; an etching process is performed to form the first gate and the second gate in the first region and the second region, respectively; Removing the photoresist layer; performing a first ion distribution process to form a lightly doped non-electrode (1 ightd) around the first gate and the second gate respectively 〇peddrai η, LDD); performing a second ion distribution process to form a first source electrode and a first non-polar electrode around the first gate electrode respectively; selecting between the first region and the second region Selectively forming a protective layer covering the first gate electrode and the second gate electrode above and the side wall, respectively; and Page 19 200409366 VI. Scope of patent application A third ion distribution process is performed to form a second source electrode and a second drain electrode around the second gate electrode, respectively. 2. The method according to item 1 of the application, wherein the surface of the substrate includes a buffer layer, and the polycrystalline stones are formed on the surface of the buffer layer. 3. The method of item 2 of the application scope, wherein the method of forming the polycrystalline silicon island includes the following steps: forming an amorphous silicon thin film on the buffer layer, the amorphous silicon thin film defining at least one of the polycrystalline silicon islands scheduled to be formed; Active region; forming a mask layer over the amorphous stone film; performing a first yellow light and etching process to remove the mask layer in the active region; performing an excimer laser recrystallization A process of recrystallizing the amorphous silicon film in the active region into a polycrystalline silicon film; and performing a second yellow light and post-etching process to remove the mask layer and the amorphous stone film. 4. The method according to item 1 of the application scope, wherein the protective layer is a metal layer. 5. The method of item 4 of the application, wherein the method of selectively forming the protective layer includes the following steps: forming a predecessor layer (p r e c u r s 〇 r 1 a y e r) covering the gate insulating layer, 200409366 6. The scope of the patent application is on the first gate and the second gate, wherein the predecessor layer will react with the metal gate to cover the first gate and the second gate and The precursor layer on the side wall reacts to form the metal layer; and the unreacted precursor layer is removed. 6. The method according to item 1 of the application range, wherein the first ion distribution process and the second ion distribution process are both N-type ion distribution processes, and the second ion distribution process is a P-type ion distribution process. Process. 7. The method according to item 1 of the application range, wherein the first ion distribution process and the second ion distribution process are both P-type ion distribution processes, and the second ion distribution process is N-type ion distribution processes. Process. 8. A method for manufacturing a low temperature polysilicon thin film transistor (LTPS TFT), the method includes the following steps: a substrate is provided, and an active area is defined on the surface of the substrate; A polysilicon island is formed in the active region of the substrate surface; a gate insulating layer is formed to cover the polysilicon island and the substrate surface; a first conductive layer is formed over the gate insulating layer; a first A yellow light and etching process to pattern the first conductive layer; and a first ion distribution process is performed on both sides of the first conductive layer Page 21, 200409366 VI. Scope of patent application Lightly doped anodes are formed in the polycrystalline silicon thin film; a second conductive layer is selectively generated on the surface of the first conductive layer and around the sidewall; and using the first conductive layer The two conductive layers are masks, and a second ion distribution process is performed to form a drain and a source on each side of the composite gate; wherein the first conductive layer and the second conductive layer are jointly formed A composite gate makes the lightly doped drain electrodes directly below the composite gate to increase the operating efficiency of the low temperature thin film polycrystalline silicon transistor. 9. The method according to item 8 of the application, wherein the surface of the substrate further comprises a buffer layer, and the polycrystalline silicon island system is formed on the surface of the buffer layer. 10 · The method according to item 9 of the application, wherein the method for forming the polycrystalline silicon island includes the following steps: forming an amorphous silicon thin film on the buffer layer, the amorphous silicon thin film is defined with at least one predetermined formation of the polycrystalline silicon island An active region; forming a mask layer over the amorphous stone film; performing a first yellow light and post-etching process to remove the mask layer in the active region; performing an excimer laser The recrystallization process recrystallizes the amorphous silicon film in the active region into a polycrystalline silicon film; and performs a second yellow light and post-etching process to remove the mask layer and the amorphous stone film. 200409366 VI. Application for Patent Scope 1 1. The method of the eighth scope of application, wherein the method for forming the second conductive layer includes the following steps: forming a precursor layer (precursor 1 ayer) covering the gate insulation Layer and the first conductive layer, wherein the predecessor layer will react with the first conductive layer, so that the predecessor layer covering the first conductive layer and the side wall reacts to form the second conductive layer. ; And remove the unreacted predecessor layer.