TW200405662A - Complementary input dynamic muxed decoder - Google Patents

Abstract

A muxed-decoder circuit including multiple complementary dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic circuit, a complementary N-logic AND dynamic circuit and a pass device. The complementary P-logic AND dynamic circuit has an output coupled to a corresponding output evaluation node, and evaluates bits of an encoded address value corresponding and bits of a digital select value having a logic state for selecting the encoded address. The complementary N-logic AND dynamic circuit has an output coupled to a corresponding preliminary evaluation node, and evaluates inverted bits of the address value and the digital select value. The pass device is coupled between corresponding the first and second evaluation nodes and drives the second evaluation node low if the complementary N-logic AND dynamic circuit fails to evaluate. The AND logic gate couples to the output evaluation nodes and provides a corresponding decoded bit.

Description

200405662 V. Description of the Invention (1) [0 0 0 1] This application claims to benefit from the following United States Advance Application: Case No. 60 / 412,110, the application date is September 19, 2002, and the case No. 60/412, 112. Application date: September 19, 2002. [0 0 0 2] This application is related to the following U.S. patent applications, which are also in the same application, with the same filing date and the same applicants and inventors: 0 Taiwan application number DOCKETNUMBER Patent name 92230292 CNTR: 220 3 Complementary Input Dynamic Logic Architecture 92123091 CNTR: 220 5 Complementary Dynamic Input Logic Architecture for Complex Logic Functions [Technical Field of the Invention] [0 0 0 3] The present invention is a field related to logic circuits, and particularly refers to logic circuits that include multiplexing. The use of demodulated high fan-in complex logic circuits. [Prior art]

Page 6 200405662 V. Description of the invention (2) [0004] Because of speed requirements, dynamic circuits are often used to implement logic functions in current pipeline systems. Figure 1 is a representation and logic function; a schematic diagram of the logic between 100 ′ and-the implementation of the demonstration and logic between 100 is shown in Figure 1, the dynamic circuit 102 and the logic _ are U inputs, respectively D1 , D2 ,, means that it also contains a p round ^ Q ,,,. The dynamic logic circuit 102 includes: a leading element 104 of the channel-at the end of the channel 7, a logic circuit that evaluates the logic function, an output buffer or inverter / drive state, and the storage side The outputs of Xiang and Erϋ are coupled to the output of u3 and vice versa. At the same time, the Q signal is established by the output of the dynamic temporary driver υι of the circuit of the anti-correlation clock signal " cu ". Dynamic logic punctuality is controlled by ^ signal. When the cu signal is invalid, the low-level temple 'dynamic logic circuit is Rong Wei ^ to the high level, the state of waiting or pre-charging; when the signal is pulled p0 source end element _ logic between. Leading component point " m ". For example, the source voltage " VDD ", the drain terminal coupled to the evaluation is the same as in this article, the terminal label and the signal loaded by the terminal are extremely light to i (use the ^ terminal / ^ load signal). The source $ of the end element $ shares a reference voltage,, GND ,, and the drain terminal is coupled to nrv, N. Time ... is implemented in the code "N" (referred to as N-logical question), and the use number-fine H element N1_NN is applied between points H1 and L0. Especially the drain terminal of the k-th component N1 is coupled to HI, while the source terminal is coupled to the next page 200405662

, The drain terminal of each channel element, and so on until the source terminal of the last N-channel π piece NN is coupled to L0. The N inputs M-DN are provided to the respective N-channel elements n1-nn. At this point the points are coupled to the inputs of the inverters and U2 and the output of the inverter element U3. [0 0 0 6] During operation, when the cl κ signal is low, the lead element is pre-charged to the logic high level to the point η I, and the signal Q is pulled to the low position via the inverter / driver to prepare for the input signal at the same time]) 1_1 ^ prepares for the evaluation of the logic function. When the CLK signal is at a high level, the logic function of the logic circuit 104 is either an evaluation failure or an evaluation failure according to the input state of D1_DN. When the logic circuit 104 is being evaluated, all the input signals M-DN are at the high level which can turn on all the N-channel elements Nl-NN. The logic circuit 104 drives the point HI to the logic low level through the activated ending element. At the same time, the output signal 9 is driven to a logic high level. Once point 01 is driven low, point HI will remain low until the CLK signal is driven low again. If the evaluation of the logic circuit 104 fails, the maintenance circuit 106 maintains the point HI at a logic high level, and the signal Q remains low. Therefore, when the CLK signal is low, the Behr Q signal is also low. If the logic function is true, when the CLK signal is high, the logic q can be used to drive the signal q to high. [0007] The logic function implemented by the logic circuit 104 is a sum function of multiple inputs. For evaluation, therefore, when the CLK signal is high, all input bellows D1 DN must also be high. The logic function is usually implemented in an N-logic gate (shown as logic circuit 104) formed by the serial connection of channel elements. In this way, there are at least two factors that cause problems in dynamic circuits. First, at our point and ⑶ point

V. Description of the invention (4) The number of counties in the evaluation path, that is, the number of inputs that belong to: the function of the line (series also ::: the number of components in the evaluation path, the function of the evaluation path needs to be evaluated and the number of inputs is also summed up) ). The long evaluation signal takes a long time to reach the destination input signal, and the larger number is second. Because N_y is used, the overall circuit speed will be reduced. Higher components are affected by the element realization evaluation function, so the element effect element in the stack becomes j. Because of the stacking relationship, the meta-stable potential energy is maintained. ^ Critical voltage change 'therefore provides the circuit's non-collective electricity [: 二 H 了 ΐϊί This problem related to the evaluation of the path length, the size of each stack of the logic two system does not exceed 4 orders of portal time and heart 丨 °: The estimation circuit is better in two levels. Resolving the evaluation path limitation 4 砀, can use the inverse function (implemented with OR logic gate term), or the feathering and function decomposition into a low fanning and function stacked in series. A, [0009] The realization of the inverse and function is related to the conversion of the series and path into an OR path (implemented with a parallel or logic gate term). When an inverted output is available, the solution of the inverted or logical function satisfies the ordinary function. However, transforming the first-level sum of logical operations into an or-term will force the or-terms in the later hierarchy to be converted into and-terms, thus making the reverse solution method unusable in a complex logic state. So this reverse method just transfers the problem of N stacking to the later logical hierarchy. [0010] FIG. 2 is a schematic diagram of an exemplary logic circuit 202 and a general decomposition method illustrating a 16-input and logic gate 2000 and an implementation and logic gate 2000. The AND gate 200 includes 16 input signals (represented by A1-A16 respectively), an output signal Q, and also considers a high fan-in and function. Use 4 lows to lose

224 200405662 V. Description of the invention (5) Fan-in levels 204, 206, 208, and 210 form a single and logic gate 200 in series. Each level contains one or more 2_ inputs and logic gates. The first level 204 contains 8 logic gates, each of which is divided into logic gates.

Do not receive the respective input signal pairs from the input signals A1-A16. The second level 206 includes 4 logic levels and each of the 2 logic levels and the output of the logic idle are regarded as its input pairs. The third level l 3 2 levels and the logic gate are each of the 2 levels and the logic level 206. And logical M ps recognizes that L 4 ^ n…: the output of the human series is regarded as its input pair. The fourth level 21 0 includes one logic gate, and the child, limb & gate 4 and logic gate take the output of the corresponding two levels of the third level 208 and logic gate as their input pairs. • All [口 〇〇〇 ^ 值 J 找 Attention is that each of the logic circuit 202 and the function ^^ 2 ^ Solid rain input 'Therefore the respective evaluation paths are decomposed into low fans causing the overall circuit delay, a The low fan-in operation of the additional series-coupling hierarchy is not good = two fan-in and the function decomposition into several orders Λ ^ ^ Ν ^ ^ ^ are not good. For the purpose of increasing the number of fans n a and ut ° of each logic gate, such a *, the number can be: salt: become 5: 4 input and logic idle, each logic gate has 4 fans. However, because each and every function has a relatively large fan-in and it also requires 2 levels, so, there is still a delay from this method. [Content of the Invention] [0 01 2] Example of the present invention φ ^ eu ^^ The multiplexer decoder circuit in the example includes a j-complement input dynamic circuit and a logic plus station 仏 X 么 铒, 铒 brake. A complementary input is used to move the circuit.

200405662 V. Description of the invention (6) are complementary to the corresponding code output bits p_logic and a lead coupled to the corresponding number. It is evaluated that there is a logic circuit for the address and responds to the clock selection. Continuity element N-logic and motion. This is related to the number of logic decoding bits. The output and coupling signals of the serial and dynamic components should be coded. The output of the component in the opposite circuit is ^ = one of the meta-coded address and its corresponding solution T. A complementary input dynamic circuit includes: one state Circuit, one complementary N-logic and dynamic circuit, two complementary P-logic and dynamic circuits have an output evaluation output point, and respond to the bits of the address value of the clock t address, and digital selection of the selection code Bit value. Complementary Logic and Dynamics: Go to one of the corresponding multiple preliminary evaluation points, evaluate the reverse bit of the address value, and couple between the first and second evaluation points of the digital selection, and when the complementary evaluation fails, Drive the second evaluation point as the input and provide countermeasures for the low-level face to the output overestimation point

[0 0 1 3] and the logic gate may be a reverse logic gate. The multiplex decoder can include one or more inverters / drivers. Each inverter / driver has an input to receive the clock signal and an output to provide the reverse clock signal to the conduction circuit. Complementary N-logic and dynamic circuits may include ^ N-channel elements coupled in parallel, and each channel element has an input for receiving a selection bit and an address bit. Complementary p-logic and dynamic circuits may include a plurality of P-channel elements coupled in parallel, and each channel element has an input for receiving a selection bit and an address bit. [0014] According to an example of the present invention, a method for selecting and decoding at least 丨 bits at a plurality of multi-bit encoding addresses includes: merging each bit of the selection value 'for selection correspondence. The address of the address "

Page 11 200405662

From N to ΞΐΪ, the number of items, the set of items, the evaluation uses a plurality of complementary mutual-logical logic = :; = the complement of the logical function of the joint, when the pair is signed to the library, a complementary N-logic circuit will be used: is is pulled to a low level at one point, the evaluation uses a plurality of ρ-logic electrical circuits to evaluate the complement, and when complementary ρ- logic uses a mother complementary p-logic circuit to pull the corresponding second evaluation point to a high level, the corresponding conduction is conducted through The components (controlled by the corresponding 1st evaluation point) will be paired. The corresponding second evaluation point is pulled to a low level, so that the evaluation of each corresponding complementary N-logic circuit fails, and the second evaluation point is combined with a logic gate to provide a decoding bit. [Embodiment] [0 0 2 6] The following description is provided in the context of a specific implementation and its necessary conditions, so that those skilled in the art can use the present invention. However, various modifications to this preferred embodiment will be apparent to those skilled in the art, and the general principles defined herein may also be applied to other embodiments. Therefore, the present invention is not limited to the specific implementations shown and described herein, but has the same features as those described herein? The widest scope of the principle of exposure is consistent with novel features. 〃 [0 0 2 7] The inventor of this application has acknowledged the necessity of implementing high fan-in complex logic functions in dynamic circuits, where this implementation is not related to dynamic logic with a large number of input entries so far The realization of the matrix effect and potential factors. The inventors have therefore developed a complementary input dynamic logic circuit which can assist the input of multiple numbers

Page 12 227 200405662

5. Description of the invention Item (8), without the matrix effect due to the high stacking or the potential factor due to the item decomposition. [0028] FIG. 3 is an exemplary complementary dynamic logic circuit 300 implemented according to an example of the present invention. The CLK signal is supplied to the gate terminals of the p-channel head element and the N-channel end element NO. The source terminal of the lead element p0 is connected to the source current VDD and the drain terminal is coupled to the first preliminary evaluation point "NT0p". The drain terminal of the end element NO is coupled to the reference point "NB〇T, ', and the source terminal is coupled to the reference voltage point GND. The complement of the logic function used to evaluate (using N-logic two and present) NC0MP 302; this logic function The output of 30 is coupled to the ⑽⑽point reference point and the NB0T point. The NC0MP 302 receives the reverse signals of N input signals ^ -⑽, which is represented by DNB: DIB, where the letter "β", except for the special description $, Refers to a logical reversal (that is, logical or true reversal is both logical 0 or no, and so on). It is worth noting that D1B-dnb and dib: dnb represent the same set of signals (N is a positive integer greater than 丨). A stored power 304 is coupled between VDD and NT0P. The example shows that the storage circuit 304 is implemented as a half-, maintenance 304. The storage circuit 304 includes: an inverter ^ and two channel 7C pieces P1. The input of inverter U1 is lightly closed to NT〇p, and the output surface is closed to the gate terminal of pi. The source terminal of element 1 is coupled to vdd and the drain terminal is coupled to NT0P. [0029] The CLK signal is also provided to another p-channel element and a wheel-in terminal of an inverter / driver. The source 3 of the p2 element is closed, the light is closed to the second or the evaluation point is turned out, ρτ〇ρ ". The opposite direction / driver sends out its output as a pulse

200405662 5. Description of Invention (9) is '' CLKB ''), and its output is coupled to the source of N-channel conduction element N1. The gate of N1 is coupled to NT0P, and the drain is coupled to ρΤ〇ρ. # NC〇Mp 302 The evaluation of the logical function complement can be implemented using p-logic (represented by pc〇Mp 3〇6) ’The reference point of PC0MP 306 is coupled to VDD, and the output point is coupled to the PTOP point. PCOMP 306 receives N input signals D1-DN, and implements them in the Π-logic " (that is, using P-channel elements), just as NC0MP 302 implements the complement of the logic function in N-logic. PT0P is provided to the input terminal of an output inverter / driver U2, and the output terminal of the inverter / driver U2 shows that its output signal is n Q ". [0030] During operation, the initial value of the CLK signal is low, so the ρτορ output evaluation point is pre-charged to a high level via the lead element P2, while the NT0p preliminary evaluation point is pre-charged to a high level via the lead element P0. The initial value of the output signal Q is also a low level. When the CLK signal is at a high level, NCOM 302 and PCOMP 306 evaluate the input signals dnB: d1b and dn: D1, respectively. This action is to calculate or control the status of NTOP and PTOP points. NCOMP 302 and? (: 0 ^ * 卩 30 6 both implement the complement of the same logical function, so when (^ [is a high level, both NCOMP 302 and PCOMP 306 are either in evaluation or the evaluation fails. When NCOMP 302 and PCOMP When both 306 are negative (or when NCOMP 302 and PCOMP 306 failed to evaluate), the logical function itself is positive. When both NCOPM302 and PCOMP 306 are evaluated, the logical function itself is not. [0031] Therefore When the logic function is true, both NC〇Mp 20 3 and pc〇Mp 306 fail to evaluate, and NT〇IM $ calculated by the maintenance circuit 300 holds a high level. Since NTOP is still high, the conducting element N1 is still conducting or open

Sun Page 14 229 200405662 V. Description of Invention (ίο) Kai. The inverter / driver UC0 sends a buffered CLKB signal to the low level. This signal discharges PT0P to the low level through the conduction element, so q becomes the high level (true), that is, the logic function is true. In this method, when the conducting π element N1 is controlled by NTOP and kept in the conducting state, the inverter uc0 pulls the evaluation point PT0P low through a maximum of 2 N-element paths, so the logic true state will be issued by the Q output signal . These two N-channel elements are explicitly n-channel elements in the range of the inverter uc0 and the conduction element N1. When the logic function is negative, the NC0MP 302 and the PC0MP 306 are evaluated, so that the NTOP is pulled to a low level by the end element NO, and 306 is pulled to a high level. The conducting element N1 is deactivated or turned off, so PTOP remains at a high level. The q output signal remains at a low level (No), that is, the logic function is No. [0032] Unlike a simple domino circuit, the complementary input dynamic logic circuit 300 allows its output to be driven to a high level during the evaluation. Unlike the domino circuit, if the input signal arrives later, when the CLK signal is high and both the NC0MP 302 and PC0MP 306 are evaluated, the output signal Q can still be driven back to the low level. The complementary input dynamic logic circuit 3 may be considered to include: a complementary N-channel logic circuit 308 related to the first preliminary evaluation point NT0P and a complementary P-channel logic circuit 310 ′ related to the second output evaluation point PT0P. The PTOP is used to develop the output signal Q via the inverter / driver U2. Complementary N-channel logic circuit 3 〇8 includes: Leading and ending elements p0 and N0, Complementary N_ logic circuit for logic function evaluation ... ⑽? 302 and the sustain circuit 304. The complementary p-channel logic circuit 31 includes: a lead element P 2 and a complementary P-logic circuit PC0MP 306 for evaluating the logic function. If two complementary logic circuits 308 and 310 are both evaluated, NT0P is driven low by circuit 308

Page 15 200405662 V. Description of the invention (11) Level, PTOP is driven to high level by circuit 310. When the evaluation of the circuit 308 is more than 31, the NTOP provides and controls the conduction element N1 to pass through a commutator, and the buffer of the CLK signal (formed by the inverter / driver) drives ρτ〇ρ to a low level. [0033] Another alternative embodiment is shown by the dashed connection in FIG. 3, the source terminal of the inverter UC0 is replaced by the N-channel N2, and the drain terminal of N2 is coupled to the source terminal of the bypass element M. The gate of n2 is coupled to the CLK signal. As a result, when CLK is at the high level, N2 is turned on and the drain of N1 is pulled to the low level. If gNC〇Mp 302 and% 〇 commit 306 evaluation failure, the low level will be transmitted to the signal ρτ〇ρ through N1, so it can provide two-level output Q. [0034] The stable reference point of the flood number TPOP is supplemented by a weak maintenance circuit including the components M and μ. Because these components are recommended but not necessary, 'they are indicated by dashed links. Replacing the semi-sustained circuit with a fully maintained circuit (see Figure 1) containing two inverters can also provide a stable reference point for PTOP. > [00 ^ 35] Another alternative pull-down element N2 can replace the inverter uc〇; the built-in M weak maintenance circuit add-on provides a stable reference point ρτ〇ρ, this method can be applied to the present invention In all examples described later. [0036] FIG. 4 is a schematic diagram of an exemplary complementary input dynamic logic circuit 400 implemented in accordance with the present invention and a more specific example of a logic function. The complementary input dynamic logic circuit 400 is generally similar to the complementary dynamic logic circuit 0, and the same components have the same designations. For the complementary input dynamic logic circuit 400, the complementary and n-logic circuit 4O2 replaces NC0pM 302, 200405662 V. Description of the invention (12) The complementary and P-logic circuit 406 replaces PC0MP3 06. In other words, the complementary input dynamic logic circuit 400 is exactly the same as the complementary dynamic logic circuit 300 except for the part that specifically implements the evaluation and logic functions. It is worth noting that as long as the inverter / driver U2 is replaced with a driver, or the buffer removes the inversion function, or another inverter / driver is added to the output of U2 (not shown in the figure), then The complementary dynamic logic circuit 400 can be converted into a circuit that performs an inverse logic function. [0037] In N-logic, N and N-channel elements NC and NCN coupled in parallel between NTOP and NBOT are used to implement complementary and N-logic circuits, and the complement of the sum function in N-logic is also realized. However, when the complement input DNB is provided, the result requires a logical sum of the D1-DN inputs. In the same way, in P-logic, N P-channel elements pen-PCN coupled in parallel between VDD and PTOP are used to implement complementary and P-logic circuits and implement the remainder of the AND function. The input signal complement DIB-DNB is provided to the gate terminals of the n-channel components N C1-NCN, respectively (for example: D1 B is provided to the gate of N C1; D2B is provided to the gate of NC2; ...), non-complement The input signals di—are provided to the gate terminals of P-channel elements PC1 to PCN, respectively (for example, j) 1 to the gate of PC1; D2 to the gate of PC2; ...). [0038] The operation of the complementary input dynamic logic circuit 400 is similar and reference is made to the operation of the complementary input dynamic logic circuit 300 described above. When any one or more of the D1_DN input signals are at the low or low level (for example: logic "0"), the complementary and logic circuits 402 and 4 06 both perform the evaluation action, so the signal corresponding to the D1B-DNB input signal is Is true or high (for example, · logic Π1Π). If the complementary and logic circuits 40 2 and 406 are both evaluated, and the function is

Page 17 200405662 V. Description of the invention (13) Second, when the CLK signal sends a high level, the _ signal becomes no (^ 氐 level). Or, when all the input signals D1-DN are true, the complementary and logic circuits 402 and 406 both fail to evaluate, so that the signals corresponding to D1B-input flood numbers are all negative. If the complementary and logic circuits; and 06 both fail to evaluate, and the function is true, so that when the clk signal is sent high, the Q output signal becomes true (high level is issued). It is worth noting that the circuit speed in Figure 4 is not sensitive to fan-in; any reasonable number of inputs and functions can be executed without reducing the speed of the circuit. This is because the evaluation path only passes through the two stacked N ^ and N1 elements in uc0. [0039] FIG. 5 is a schematic diagram of an exemplary complementary input dynamic logic circuit 500 implemented in another or more specific example of the implementation of a logic function according to the present invention. Complementary input dynamic logic circuit 500 is generally similar to complementary dynamic logic circuit 300 (the same components use the same designation), except that TNC〇pM 302 is replaced by complementary or N-logic circuit 502, and PC〇Mp 3 〇6 is replaced by complementary or p_ logic circuit 506. In other words, the complementary input dynamic logic circuit 500 is exactly the same as the complementary dynamic logic circuit 300 except for a part that specifically implements the evaluation or logic function. [0040] In the logic, a complementary or n-logic circuit 502 is implemented using N N-channel elements NCI-NCN coupled in series between NTOP and NBOT. It also implements the complement of the OR function driven by the complement input D1B — DNB in N-logic. In the same way, in p-logic, a complementary OR p-logic circuit 506 is implemented by using N P-channel elements pC1-PCn coupled between VD]) and PTOP. It also implements the complement driven by the true input D1_DN in the OR function.

Page 18, 200405662 V. Description of the invention (14) Therefore, the 'input signals D1B-DNB are provided to the gate terminals of the N-channel elements NC1-NCN, and the input signals D1-DN are provided to the p-channel element P C1, respectively. -The brake extreme of PCN. [0 041] When all D1-DN input signals are NO, the complementary or logic circuits 502 and 506 both perform the evaluation action, and the signal corresponding to the D1B_DNB input signal is true. If the complementary OR logic circuits 502 and 506 are both evaluated, the OR function is negative, so that when the CLK signal is pulled to a high level, the Q output signal becomes no (and a low level is issued). Conversely, when one or more of the input signals D1-1 ^ are true, the complementary or logic circuits 502 and 506 both fail to evaluate, and

The signal corresponding to the DIB-DNB input signal is NO. If the complementary and logic circuits 40 2 and ^ 06 both fail to evaluate, or the function is true, so that when the clk signal is pulled to a high level, the Q output signal becomes true (the high level is claimed). [0042] When using the complementary input dynamic logic circuit 30 () and its related forms such as the complementary input dynamic logic circuit 400, many benefits and points can be obtained. The complementary input dynamic logic circuit 300 is particularly suitable for use in high fan-in and decoding circuits. As mentioned above with reference to the discussion of FIG. 4 1-L § ^ # 1 ^ 3〇 ° ^ 4 00 ^ ^ ^ Hilf ^ ^, =, pieces: so it will be more than other logic power provided before this

Section 2 is more than the current technology used by the car parent to achieve high fan-in and function decomposition. The dynamic logic circuits 300 and 400 are faster than other circuits. 502 and 506 are complementary or logical circuits of complementary input dynamic logic circuits. 502 and 506 are N-channel disks P— 通 增 — 从 芙 # 效应 # h π Γ t1 pieces of stacked type, so the number of fans will be limited due to ^ matrix effect and potential factors. [0043] FIG. 6 is an exemplary complementary input operation for implementing a complex logic function

$ 19 pages 200405662 V. Description of the invention (15) A schematic diagram of the state logic circuit 600. The complementary input dynamic logic circuit 600 has a similar graphic structure as the complementary input dynamic logic circuit 300, and will appropriately provide implementations that approach three to four or terms, each of which includes a high fan-in Logic and functions. The complex logic function implemented by the complementary input dynamic logic circuit 6 00 has complex and / or functional form Equation 1 as follows: Q = D11, D12 · ~ D1X + D21 * D22 · ... D2Y + ... + DM1, DM2 •- DMZ (1) where π · '' represents logic and function, and represents logical OR function. Equation 1 is the logical OR of multiple inputs and terms. It usually appears in the operations of pipeline execution systems. The first term has "X" and terms: Dll, D12 ..... D1X; the second term has π Υπ and terms: D 2 1, D 2 2, ..., D 2 Υ; and so on to The last or M term (the last term) has a total of π Zπ and terms: DM 1, DM2, ..., DMZ. [0044] The complementary input dynamic logic circuit 600 has a total of M complementary N-channel dynamic logic circuits. Each is very similar to the complementary N-channel logic circuit portion of the complementary input dynamic logic circuit 300. The first complementary N-channel dynamic logic circuit 602 implements the first sum term 'and Γ (D21, D22, ..., D2Y), and its circuit includes: a P-channel head element P1 0, an N-channel The ending elements N1 0, one, and one are labeled N-logic block 604 and a storage circuit si. The CLK signal is provided to the gate terminals of components P10 and N10, and the reverse input signal]) ilB-〇1 乂 6 (that is, 〇118: 〇116) is provided to the respective inputs of ^ 1-logic block 604. The source terminal of the lead element P10 is coupled to VDD, and the drain terminal is coupled to the first preliminary evaluation point NTOP1. The source terminal of the end element N10 is coupled to GND.

Page 20, 200405662 V. Description of the invention (16) The extreme surface closes to the first reference point ΝΒΟΊΊ ° The output of the N-logic block 604 is coupled to the NT0P1 point, the reference point is coupled to the NB0T1 point, and the configuration method of the N-logic circuit 402 Similarly, they all include X N-channel elements arranged in parallel, and the gate terminal of each N-channel element can receive a respective reverse input signal in D1XB: D11B. The storage circuit S1 is implemented as a semi-maintenance, and, like the storage circuit 304, includes: an inverter un and a p-channel element pii that is planar between VDD and the point NTOP1.

[0 045] In the complementary input dynamic logic circuit 600, the type of the remaining M-1 complementary N-channel dynamic logic circuits used to realize the remaining and terms is the same as the first complementary N-channel dynamic logic circuit 6 〇2 is the same. As shown in the figure, the last (or M) complementary N-channel dynamic logic circuit 606 realizes the last sum term n ANDMn (DM1, DM2, ..., DMY), and its circuit includes:

The channel head element PM0, an N-channel end element question 0, an N-logic block 608 marked with ANDM, and a storage circuit SM. The CLK signal is provided to the gate terminals of the components PM0 and NM0, and the reverse input signals DM1B—DMZB (ie, DMZB: DM1B) are provided to the respective inputs of the n-logic block 608 of the μ-logic block 608. The source terminal of the lead element PM0 is coupled to O1), and the drain terminal is closed to the final preliminary evaluation point NTOPM. The source terminal of the end element Q is coupled to GND, and the drain terminal is coupled to the final reference point Nβ〇TM. The output of the N-logic block is coupled to the NTOPM point, and the reference point is coupled to the 〇001 ^ point, which is the same as the assignment method of the N-logic circuit 2. They both contain 2 channel elements arranged in parallel. 'Each N-channel element The gate terminals can each receive a reverse input signal from dmxb:]) M1b. The storage circuit SM is treated as half-maintained and the storage circuit 304 is the same, and includes: an inverter UM1 and an on-chip inverter.

Page 21 200405662 V. Description of the invention (17) P-channel element PM1 coupled with the point NTPO.

[0 046] M preliminary evaluation points NT0P; i-ντορμ are respectively closed to the respective gate terminals of the M P-channel elements P21-P2M, and are also coupled to each of the M N-channel conduction elements N11-NM1. Self brake extreme. The ρ-channel element ρ21_ρ2M is faced in series or ρ-stacked between VDD and the output evaluation point ρτορ. Especially the drain terminal of the first P-channel element P21 is coupled to the point ρτ〇ρ, the source terminal is coupled to the drain terminal of the second P-channel element P22 (not shown), and the second P-channel element P22 The source terminal of is coupled to the drain terminal of the third p-channel element P23 (not shown), and so on, and the source terminal of the last p-channel element P2M is coupled to VDD. The N-channel conduction element Nη_NM1 is coupled in parallel between the TPOP and the output of an inverter / driver jjco. The inverter / driver UC0 provides a reverse clock signal CL0 at point CLKB. In particular, the drain terminal of each N-channel conduction element Nn —〇} is coupled to the ρτ〇ρ point, and the source terminal is coupled to the inverter / driver uc〇 so as to receive a “signal. The input of the inverter / driver UC0 can be The CLK signal is received, and its output provides the CLKB signal. The input of an output inverter / driver U2 is coupled to the PTOP point 'and its output provides an output signal 卩.

[0047] The operation method of the complementary input dynamic logic circuit is described below. When CLKrfL is at a low level, each preliminary evaluation point NT0ρ1-Nτ〇ρM is pulled to a high level through the lead element P10-PM0, so that each N-channel conduction element Nil-NM1 starts to operate. The inverter / driver uc〇 sends the CKLB signal to the high level, and PT0P is charged to the high level in advance, so the initial value of the q output signal is the low level. Because N-logic blocks ανμ-ΑNM are coupled in parallel ’, so when the CLK signal is at a high level, each N-logic block

_ Painting_ Page 22 200405662

AND1-ANDM evaluate their respective input signals simultaneously. If the evaluation of one of the N-logic blocks AND1-ANDM fails, because of the operation of the corresponding storage π piece SI-SM, the corresponding evaluation NT〇IM-NT〇pM maintains the sub-standard and maintains the corresponding N-channel conduction element Action of NU-NM1 ^ When one or more N-channel conducting elements are turned on because the CL0 signal is low, the inverter / driver UC0 discharges the PT0P point to a low level, so that the output signal is a high level (true) . This situation occurs when one or more of the N-logic blocks AND1-ANDM's reverse inputs are negative (meaning normal, all non-reverse 1 inputs are true), so the complex logic function is true. If n — logic blocks AND1-ANDM are evaluated, N-channel conduction elements NU-NM1 are all turned off, P-channel elements P21-P2M are all turned on and ρτορ is pulled to a high level, so the Q output signal is a low level (No). When at least one inverse input of each logic block ^ ANDM is true (meaning the corresponding normal state, the non-inverting input is no), then the latter situation will occur, so the complex logic function is not.

[0 048] As compared to the complementary input dynamic logic circuit 300 in FIG. 3, unlike the implementation of the complex logic function complement in P-logic, the complementary input dynamic logic circuit 600 uses each initial evaluation point NT0P and NT. PM's point of view. Especially in ordinary complementary circuits, it can be observed that the logical implementation of p_logic complementation that is desired to be represented is evaluated logically to achieve an alternative representation of the logical function complementarity. Therefore, the NT0P1-NT0PM points are used as the P-logic stack input of the p-channel of the calculation output evaluation point ρτορ, instead of implementing the logical complement of each of the P-logical AND terms (each and term may include parallel P-channel element). Therefore, M complementary P-logical blocks (one block represents one and

Page 23, 200405662 V. Description of the invention (19)-each item can be replaced by a single _ p ~ channel element, 1 a P-channel element P2 1-P2M has a gate terminal corresponding to one Evaluation points NT0P1-NTTOPM drive. This synthetic pattern can be effectively simplified. [0 049] Complementary input dynamic logic circuit 600 does not require stacked components in the N-channel evaluation path of the N-logic block .M-ANDM. For example, the configuration of the complementary input dynamic logic circuit 300 in the N- and p-channel evaluation paths may require stacked components to obtain each additional or term in a complex logic function. However, the complementary input dynamic logic circuit 600 does have a stack of P-channel elements P2 and P2M in the p-channel evaluation path, so the maximum number of OR terms will be limited due to the leakage factor and the matrix effect. The number of items in the examples is limited to approximately 3-4 items. For the simplified circuit, the complementary input dynamic logic circuit 600 is slightly slower than the complementary input dynamic logic circuit 300. This is because the N-logic side all evaluates the priority and drives the PTOP point. Compared with today's dynamic circuits that implement complex functions, the method using complementary input dynamic logic circuit 600 as an example is faster than other methods. [0050] FIG. 7 is a simplified block diagram of a complementary input dynamic logic circuit 700 using multiple complementary input dynamic logic circuits 702, 704, ..... 706. Each multiple complementary input dynamic logic circuit is the same as a complementary input dynamic logic circuit 600 that implements a complex logic function with multiple sum terms. The first logic circuit 7 0 2 calculates the following two terms, including the first term having "a π sum terms: d 11, 1) 12 ..... D1A and the second term having" B, "and sum terms: D21, D22, ... D2B. The second logic circuit 704 computes two other terms, including the third term with C and terms. D31, D32, ..., D3C, and the fourth term with ‘’ D " and

Page 24 200405662 V. Description of the Invention (20) Item: D41, D4 2, ... D4D. By analogy, the last logic circuit 706 runs the last two items of M and N, including " γπ and 2π sums respectively. In order to obtain the best results, each complementary input dynamic logic The circuits 702-706 all have only 2 sum terms. [0051] The outputs of the complementary input dynamic logic circuits 702-706 are provided to the inputs of respective OR logic gates, which determine the final output value Q. As shown in the figure The logic circuit 702 provides one of the inputs of the OR logic gate 700, and the logic circuit 704 provides the output Q34 to the other input of the OR logic gate 700, and so on to the last logic circuit 70. Provide another input to pull out the QMN to OR logic gate 708. Those skilled in the art should not perceive, because there is no need to consider the element's matrix effect or potential factors: Logic gate 7 0 8 can be easily input with the required It can be implemented in number, and any number of complementary input dynamic logic circuits can be stacked in parallel. For example, or logic gate 708 can be realized by parallel coupling of N-channel elements (pictured: shown), each one Each channel element receives the corresponding output from the input dynamic logic circuit 702-7007. Word [0052] The complementary input dynamic logic circuit 300 is very suitable for continuous logical operations where f is required logically and in the order of operations during operation. ^ 2. Yan Figure 8 is a block diagram of a commonly used multiplexing decoder 800. The multiplexing solution is used to select between two sets of address bits in the pipeline system and two of the selected sets are decoded. And operation examples. As shown in the figure, two sets of ^ 802 and Yu B [Z: 〇] are provided to the inputs of the respective 2_bit multiplexing Is 8 0 2. The figure group can be Λ : Examples show that the 2-bits of each address are familiar to those who are familiar with it.

Page 25 200405662 V. Description of the invention (21) The encoders must be at least 2-bits. A selection signal SEL is provided to the first selection input of the multiplexer 802 and to the input terminal of the inverter ^. The output of the inverter Η is provided to another selection input of the multiplexer 802. The state of the sel signal is used to select between coded addresses A [1: 〇] and B [1: 〇]. The selected bit (indicated by the signal ENCODED [1: 0]) is provided to the input of the decoder 804. The decoder 804 decodes ENCODED [1: 〇] into the output signal DEC〇DED [3: 0 ]. 53. Those skilled in the art can perceive that decoding includes bits that include parallel logic and operations to determine the state of each decoded output decoded [3: 0]. For example, the state of the edc〇ded [〇] signal is related to its operation mode as shown in the following Equation 2: ENC0DED [1] B · ENCODED [0] B (2) where: the symbol π · " means Local and function, the letter "B" appended to the signal name indicates the logical inversion described previously. If the SEL signal is sent, then the A [1: 0] signal is selected by the multiplexer 802 as the ENC〇DED [1: 〇] signal. If the SEL signal is denied, the B [1: 0] signal is selected. It is also a logical operation. [0054] FIG. 9 is a schematic diagram of an exemplary complementary input dynamic multiplexing decoder circuit 900 that calculates the decoding state of the uppermost decoding bit or the * decoded [3] signal. The complementary input dynamic multiplex decoder circuit 900 includes first and second complementary input dynamic logic circuits 902 and 906, complementary input dynamic logic circuits 9 0 2 and 9 0 6 and the complementary input dynamic logic circuit 4 mentioned previously. 〇〇 achieved the same way. Especially the complementary input dynamic logic circuit 902 is similar to the complementary input dynamic logic circuit 400, except that: the conducting element ... is renamed to N4;

Page 26, 200405662 V. Description of the invention (22) Signals / points NTP0, NB0T, CLKB, and PT0P are renamed NT0P1, NB0T1, CLKB1, and PT0P1 respectively; they are coupled in parallel with three N-channel elements N1, N2, and N3 The formed and N_logic circuit 402 is implemented as an N-logic circuit 903; and the P-logic circuit 406, which is coupled in parallel with three P-channel elements pi, P2, and P3, is regarded as a P-logic circuit 904 is implemented; storage circuit 304 is replaced by the same storage circuit 905 replaced; inverter / driver U2 is removed or replaced with a 2-input inverse logic gate / driver U4. The PTOP1 signal is supplied to an input of the inverse logic gate / driver U4. [0 055] The complementary input dynamic logic circuit 906 is also similar to the complementary input dynamic logic circuit 400, except that: the conducting element ... is renamed to N9; the signal / point NTOP, NBOT, CLKB, and PTOP are renamed to NTOP2, NBOT2, respectively CLKB2 and PTOP2; 3 N-channel elements N6, N7, and N8 are coupled in parallel and N-logic circuit 402 is implemented as N-logic circuit 907 'with 3 P-channel elements P9, pi, with? The 11-coupled and p-logic circuit 406 is implemented as P-logic circuit 908; the storage circuit 304 is replaced by the same storage circuit 909; the inverter / driver ... is removed, or Replace with a 2-input inverse logic gate / driver U4. The ρτ〇ρ2 signal is provided to an input of the inverse logic gate / driver U4. [0 0 56] As shown in the figure, the complementary input dynamic logic circuits 902 and 906 provide respective reverse clocks CLKBi and CUB2 for the reverse CLK signal and the distribution pattern, so they respectively include corresponding clocks. Inverter / Driver UCQ * UC3 ,. It is noticeable that a single clock buffer circuit can be used instead of the single buffer and reverse clock signal provided to each conducting element

Page 27 242 200405662 V. Description of Invention (23).

[0057] The gate terminal of N-channel element N1 receives a reverse SEL signal (or written as SELB). The gate terminals of N-channel elements N2 and N3 respectively receive a reverse A0 and A1 signal (or written as A0B and A1B). In this way, the complementary input dynamic logic circuit 902 can obtain a logic value of 3 £ [* person 0 * person 1. The gate terminal of the channel element N6 receives the SEL signal. The gate terminals of N-channel elements N2 and N3 respectively receive a reverse B0 and B1 signal (or written as BOB and B1B). In this way, the complementary input dynamic logic circuit 9 02 can get the logic value SELB · B0 · B1. Therefore, the complementary input dynamic multiplexer circuit 900 determines DEC0DED [3] = ENC0DED [1] .ENCDDEDfO]. The complementary input and the dynamic multiplexer circuit 900 are inversely inverted to the output of the logic gate / driver U4. Claim 0

[0 0 5 8] A and B address bits are decoded in parallel. The state of the SEL signal determines which of the decoded a or b outputs is selected and supplied to the inverse logic gate U4. If the SEL signal is issued (SELB is invalid), then the human bit of the complementary input dynamic logic circuit 902 is selected, and then the comparative complementary input dynamic logic circuit 90 6 evaluates the drive pT0p output evaluation point to a high level. And if the A0 and A1 signals are high level, the conduction element N4 is turned on, and the CLKB1 signal drives the PT0P! Output evaluation point to be a low level. Cause 3 The DEC0DED [3] output signal is sent to a high level. ', 疋 [0059] In a full-speed multiplex negative encoder that calculates all bits DECODED [3: 〇], the complementary input dynamic multiplex decoding circuit 900 is overwritten 4 times (one bit overwrite-time)' Address bits are provided to the evaluation path _ P-channel ^ input, the evaluation path is due to its appropriate special solution ^

Page 28

Z4 J 200405662 V. Description of the invention (24) It is selected by bit. The lower bits DECODED [2: 0] are provided by performing a logical sum of the input bits and their complements. For example, in order to understand the DEC0DED [2] bits, the complementary input dynamic multiplexing decoding circuit 900 is overwritten, and the input signals are substantially the same except for the address bits that are exchanged. Especially A0 / A1 and A0B / A1B exchanges, B0 / B1 and B0B / B1B exchanges (that is, not A0B but A0 is provided to the channel element) ^ 2's gate extreme; not A0 but A0B is provided to the p-channel The intermediate terminal of element 4; not A1B but A1 is provided to the gate terminal of the N-channel elements; not A1 but A1B is provided to the gate terminal of P-channel element P5; not B0B but B0 To the gate terminal of N-channel element N7; not B0 but β〇B is provided to the gate terminal of P-channel element P10; not B1B but ... provided to the gate terminal of N-channel element N8; not β1 and It is B1B provided to the gate terminal of P-channel element P11). [0060] Additional bits can be used to add additional N-channel and P-channel elements to their respective evaluation paths to decode (that is, between points NTTOpx / ΝΒΟΤχ and points VDD / PTΟΡχ respectively; where " χ " Represents the number of complementary input dynamic logic circuits in parallel). A multiplexing function can be added to select from more than two input sets, and the increase method is to use: in the parallel N-channel and P-channel elements of the respective evaluation circuit $, add the parallel decoding hierarchy and the input logic of the selection signal combination. [0061] The reverse logic gate U4 can be implemented in the same manner as the complementary logic dynamic logic == 400, that is, using sufficient inputs and inverses: 1 times the number is also used. Inverter / driver U2 is replaced by non; 5 & κ β ~ wind and reverse driver (not shown in the figure)

Page 29 244 200405662

(Shown); or add another inverter (not shown) to the output to achieve the purpose of reverse output. Those skilled in this field will notice that because of its high fan-in characteristic, using complementary input dynamic logic circuit 4 00 as ",, output and logic gate can help any number of addresses (for example: 4 to [0062] FIG. 10 is a solution using complementary input dynamic logic circuits to solve four 4-bit addresses A [3: 〇], B [3: 〇], (: [3: 〇], and 1) [ 3: 〇] 's simplified block diagram of the demonstration co-speed dynamic, evening decoder 1 000. Dynamic multiplex decoding Cen 1000 contains 16 complementary input dynamic multiplex decoding circuits ⑽, MD14,, MD0 (or written as md [15: 0]), each complementary input dynamic multiplexing decoding circuit decodes each of the 16 output decoding bits DECODED [1 5: 0] separately. In addition to the additional included for selection from the majority of addresses Outside the mutual input dynamic logic circuit, each complementary input dynamic multiplex decoding circuit MD [15: 0] is implemented in the same way as the complementary input dynamic multiplex decoding circuit 9 00. At the same time, at each complementary input dynamic multiplexing &Quot; a in the decoding circuit a complementary input dynamic logic circuit containing additional N The __ channel and p ~ ^ channel elements (in the corresponding N-logic and P-logic circuits) are used to decode ^ plus ^ selection and address bits. [0063] Each complementary input dynamic multiplex decoding circuit j 5: 〇] are very similar, so only the first multiplexing decoder circuit is shown here.

Section. Address, select bits: A [3: 0], B [3: 0], C [3: 0], D

[3: 0] and SEL [1: 0], and the corresponding reverse address and selection bit: a =: 〇] B, B [3: 0] B, C [3: 0] B, D [ 3: 0] B and SEL [l: 〇] are provided to each complementary input dynamic multiplexing decoding circuit 〇 [丨 5 ·· 〇]. many

Page 30, 200405662 V. Description of the invention (26) The industrial decoder circuit MD15 includes 4 complementary input dynamic logic circuits 1002, 1004, 1006 and 1008. These 4 complementary input dynamic logic circuits 1002 , 1004, 1006 and 1008 provide 4 output evaluation point outputs PT1, PT2, ρτ3 and pT4 respectively according to the inputs of the 4-input BADB logic gate 1010. The output of the inverse logic gate 1 provides the uppermost decoding bit DEC0DED [j5].

[0 064] The multiplexing function uses 2 selection bits at 4 bits a, b, c, D

Selection, where: * SEL1 * SEL〇2 are all issued (via logic circuit 1 002), then address A is selected; * SEL1 is issued and SEL〇 is invalid (via logic circuit 1 004), then address B is selected; If SEL1 is invalid and SEL0 is issued (via logic circuit 1 006), then address C is selected; gSEL1 * SEL〇2 is invalid (via logic circuit 1 008), then address 0 is selected. Therefore, the address A bit is provided to the logic circuit 1 002, the address B bit is provided to the logic circuit 1 004, the address C bit is provided to the logic circuit 1006, and the address D bit is provided Provided to logic circuit 1 008. Each N-channel and P-channel contains 6 π pieces (2 select bits and 4 address bits). The selection of each evaluation path and the special combination of address bits are based on the decoded special output bits-»53r -4W w v

[0065] According to an example of the present invention, a dynamic multiplexing decoder is implemented by using a complementary input dynamic logic circuit. Therefore, in comparison, a complementary input kinetic energy decoding circuit 900 will be more commonly used than a commonly used multiplexing decoder (such as multiplexing; 8). 〇) Fast. According to the example of the present invention, the multiplexing decoder is complementary, and the number of decoding bits of the state logic circuit can be expanded by Gu Yi to be expanded to select from more than two sets of decoding inputs. [00 66] In the decoder example, n encodings

Page 31, 2004,056,62 5. Description of the invention (27)

Each N address has M address bits, which generates 2M decoded output bits, where M is an integer greater than 1. Provide all 2 „dynamic multiplexing ::: packets :: select from the decoded bits and select the selected bits: code: -N complementary complementary dynamic logic circuits for the first decoded bit. / 入 & The device contains: Please complement the input dynamic logic circuit: 'Group. A dynamic multiplexing decoder has 2 groups per kilogram to receive-the bit of the address and the inverse of the address = the code is decoded to determine the Its address or its inverse copy is included in the special bit evaluation path or the ρ-channel evaluation path. /, 彳 -channel [0067] Going one step further, ρ selects bits that are sufficient to edit bits from N (Integer selected in the address) Example, == 0, and:… ㈣ or… when 5 ~ 8 bits are inferred. A P-selection bit is provided to each p-channel of each complementary class A circuit. In the N-channel path, each of the dynamic I and logical complementary input dynamic logic circuits evaluates the address of a special combination or logical state that is determined by complementary input and logic. For example, such as complementary input dynamic multiplex decoding丄 1 processing, the SEL signal in the p_ channel evaluation path Ul series circuit 9 0 2 this is missing the corresponding The N-channel evaluation path is provided with the reverse secondary address, so the logic state of the B-bit SEL / SELB is reversed in the complementary input dynamic logic. The T-selection bit tl [00 68] Although the present invention As far as possible, some methods have been mentioned and the details that can be considered are described in detail, but the "formula 200405662 V. Invention description (28) may also be worth considering at the same time. For example, the state of an output signal may be reversed depending on its use in a logic circuit. In addition, although the application considered in the present disclosure is a metal-oxide-semiconductor (MOS) type device (including complementary MOS elements, and the like such as: NMOS, pMOS transistors), it can also be The same applies to analogic types such as technology or types, such as bi-amplitude elements. [0 0 6 9] Finally, those skilled in the art can perceive that the disclosed concept can be quickly used, using this specific example as the basis for the design or modified structure, and get the same as the present invention The purpose without departing from the spirit and scope of the present invention is the same as the scope of the patent application.

200405662

[Brief description of the drawings] [0015] The foregoing and other benefits, features, and advantages of the present invention will be better understood after combining the following description and the attached drawings.

[0016] FIG. 1 is a schematic diagram of an exemplary circuit using an N-input and logic gate to represent a and logic function and its corresponding implementation of N-input and logic gate; [0017] FIG. 2 is a 16-input and logic gate and A schematic diagram of a demonstration circuit that realizes the general decomposition method of 16 ~ input and gate;

[0018] FIG. 3 is an exemplary complementary input dynamic logic circuit implemented according to an example of the present invention; [0019] FIG. 4 is an overview of an exemplary complementary input dynamic logic circuit implemented according to a more specific and logical function implementation example [0020] FIG. 5 is a schematic diagram of an exemplary complementary input dynamic logic circuit implemented according to another example implemented by a specific or logical function; [0021] FIG. 6 is an exemplary complementary input dynamic logic implemented according to another example of a complex logic function Circuit outline diagram;

[0022] FIG. 7 is a specific block diagram of a complementary input dynamic logic circuit that implements a complex logic function with multiple numbers and logic gate terms including a plurality of complementary input dynamic logic circuits. Most of the complementary input dynamic logic circuits in this figure are similar to the complementary input dynamic logic circuit of Fig. 6; Fig. 8 is a block diagram of a common multiplex decoder, which is generally used in a pipeline system, and selects bits between 2 sets. An example of the subsequent and operation of the address bit and the bit selected for decoding. ", [0 024] Fig. 9 is an example of determining the decoding status of the highest decoding bit

200405662 Schematic description of the schematic diagram of the complementary input dynamic multiplex decoder circuit; [0025] FIG. 10 is a specific block diagram of an exemplary fast dynamic multiplex decoder using a mutual dynamic logic function. Description of drawing number 1 0 2 Demonstration dynamic circuit 104 Evaluation logic logic circuit 1 0 6 Storage or storage circuit 202 Demonstration logic circuit 2 0 4, 2 0 6, 2 0 8, 2 1 0 Low fan-in level 302 uses N- Complement 304 of the logical function for the evaluation of the logical implementation 304 Storage circuit 30 6 Complement of the logical function for the evaluation by the P-logic 308 Complementary N-channel logic circuit 310 Complementary P-channel logic circuit 402 Complementary and N-logic circuit 406 Complementary and P-logic circuit 502 complementary or N-logic circuit

506 Complementary or P-logic circuit 602 First complementary N-channel dynamic logic circuit 6 04 and 1-marked N-logic block 606 The last (or M) complementary N-channel dynamic logic circuit 6 08 N marked with ANDM -Logic blocks 702, 704, 706 multiple complementary input dynamic logic circuits

Page 35 200405662 Brief description of the diagram 802 2 -bit multiplexer 8 0 4 Decoder 902 First complementary input dynamic logic circuit 904 P-logic circuit 906 Second complementary input dynamic logic circuit 908 P-logic circuit 1002, 1004 , 1006, 1008 complementary input dynamic logic circuit 1010 4-input BADB logic gate

Page 36

Claims (1)

200405662 June 1 Scope of patent application-A multiplex decoding circuit, including at least: a plurality of complementary dynamic input circuits, each of which corresponds to at least one of a plurality of multi-bit coded addresses, and one of a plurality of solution bits The complementary input dynamic circuit includes: a complementary P-logic and dynamic circuit whose output is coupled to one of a plurality of corresponding output evaluation points, and the circuit is used to evaluate a bit corresponding to an address value of the plurality of encoded addresses And a bit that evaluates a digital selection value with a logic state to select the corresponding coding address that responds to the clock signal; a complementary N-logic and dynamic circuit whose output is coupled to a corresponding number of preliminary evaluation points One, the circuit is used to evaluate the reverse bit of the address value according to the clock signal response, and to evaluate the digital selection is worth the reverse bit; and a conducting element, the element is coupled to the corresponding second evaluation point and Between the corresponding first evaluation points, when the complementary N_logic and dynamic circuit evaluation fails, the conducting element drives the corresponding second The estimation point is at a low level; and the logic gate has a plurality of inputs, each input is coupled to one of a pair of output evaluation points, and one output is used to provide one of a pair of decode bits. . 2. The device according to item 1 of the scope of application, further comprising at least one inverter / driver. The inverter / driver has an input to receive the clock signal and an output to provide a reverse clock signal to the conduction. element. 3. The device according to item 2 of the application scope, wherein the conducting element includes _ Page 37 200405662 VI. Patent application scope N-channel conduction element, the N_channel conduction element has-the gate the corresponding preliminary evaluation point 'drain terminal is coupled to the pair of libraries :: close to point, source terminal is coupled to the inverter The evaluation of the round V of the driver / driver 4. The device according to item 2 of the application, wherein the at least device / driver includes a plurality of inverters / drivers, and one inverter corresponds to the plurality of complementary input dynamics The logic circuit counter-drives the input dynamic logic circuit. The output side is matched to: a device described in item ^. Each coded address has M bits to select and decode a pill. Compared to a positive integer of j, the digit selection value includes P selection bits; t is a straight integer—steps. A positive integer contained in .0 is enough to select from the N addresses. Further, the Ϊ ί ί complements The input dynamic circuit contains 2M groups of N complementary input motions. Each of the ΓM groups in the if are decoded into a pair of detailed solution Naruto & ^, each of the parent groups contains at least N preliminary evaluation points. With N output evaluation point sets; and dry estimation point set combinations And: The pair J is like one, and each and the logical closure material corresponds to a set of N output evaluation points corresponding to the input planes σ to, and the time coupling corresponds to one of the M decoding bits. Η There is an output & device for the item 1 wherein the complementary N-logic and dynamic restoration element are coupled between the corresponding preliminary evaluation point and the corresponding complex reference point, and there is one of the N_channel element. The output receives a selection bit and an address bit; Page 38 200405662 6. The scope of patent application is to take the lead in 7L pieces, receive the clock signal and couple it to the corresponding preliminary evaluation point. When the clock signal is at a low level, charge the corresponding preliminary evaluation point in advance; and receive a final file. The clock signal is coupled to a corresponding reference point; wherein the leading and trailing elements react to the clock signal to drive the evaluation of the plurality of N-channel elements. 7. The device according to item 6 of the application scope, wherein: the lead element includes a P-channel element whose source terminal is coupled to the ground point, the gate terminal receives the clock signal, and the drain terminal is coupled to the corresponding preliminary evaluation point. The terminal element includes an N-channel element, the source terminal is coupled to the terminal, the gate terminal receives the clock signal, and the drain terminal is coupled to the corresponding reference point. 8. The device described in item 6 of the ΓΓΓ range further includes a sustain coupling between the source voltage and the corresponding preliminary evaluation point. 9. ΐ :: ϊ The device according to item 1, wherein the complementary P-logic dynamics 5 P-links, and the components are coupled in parallel to the corresponding output evaluation point and the source voltage-address bit; and #output receive — Select bit and one: first receive the clock signal and couple it to the corresponding output evaluation point. When the clock signal is at a low level, the second evaluation point is evaluated, and when the clock signal is at a high level, “multiple output P- Channel element evaluation. 200405662 6. Scope of patent application w. As in the 9th scope of the application scope, +, ^ ^ p-channel element, its device is 4 ^, and the lead element contains-clock signal, no extreme The source voltage and the gate terminal receive the 11 · As in the application scope item i: up to the corresponding Λ out of the evaluation point. Reverse logic gate. The device ^ of the eight and the logic gate contains-12 · The complementary multiplex decoding circuit contains: a plurality of complementary rounds & Afc a plurality of multi-bits' = each of the circuits is about-corresponding to a plurality of decoding Bit = bit: of: all at the same time-corresponding to include: one, the mother and a complementary input dynamic circuit complex number 2 ί T, contains a plurality of parallel coupled to the source voltage and the corresponding contains a plurality of plural = estimated point Pθ1 1 " —channel components, multiple inputs that simultaneously receive multiple selections and address bits · An N-logic circuit contains a pull-in, a number of ^ 3, a plurality of ^ 3 are coupled in parallel to a corresponding plurality = ^ One of the points corresponds to one channel element corresponding to a plurality of reference points, and also includes a plurality of inputs for receiving a plurality of selections and the inverse of the address bit; two leading elements are coupled to the output and coupled to an ending element For the corresponding reference point of the P logic circuit, the first lead and tail components respond to the clock signal in order to charge the output of the N-logic circuit one in advance while driving the N-logic circuit. Evaluation; a second lead element is coupled to the corresponding output evaluation point, and the lead element responds to the clock signal so as to precharge the corresponding output evaluation point while driving the P-logic circuit evaluation; Page 40 11 ^ 200405662 6. Scope of patent application-::: Close to: Correspondence evaluation point and control with the corresponding preliminary sweat evaluation point, when the N-i Luo Xi Λ, the logic circuit evaluation fails, Connect: = ΐ low level; and an output logic gate with -output and complex, each input is coupled to one of a plurality of output evaluation points. 13. The device described in item 12 of the scope of application, which is further improved. A clockwise inverter / driver, wheel wheel 1 2 3. Provides a corresponding reverse clock signal to receive and close the clock. The signal 'output 2 = piece contains an N_ channel conduction element, which is driven by the closed-end surface:': The sub-estimation point 'the source is extremely coupled to the output of the clock inverter / f' has no extreme turn The corresponding output evaluation further includes: a corresponding preliminary evaluation, wherein the first extreme is coupled to the corresponding second P-channel receiving the ending meta-site in the pulse, and the gate reference point. Select and include from the device: the device is connected to the device ’whose source terminal contains the gate terminal, which is connected to the corresponding address method, between the estimated points. A lead element source voltage, a gate preliminary assessment of a track element, its number, and a drain terminal element include an N-terminal receiving the position selected at that time 1 4 · As in the application scope 1 2 -Maintain circuit coupling 2 15 · As in the application scope 12 It includes a first P-way terminal to receive the pulse point, wherein the second source terminal is coupled to the source surface and the corresponding output channel element, and its source pulse signal, the drain terminal 3 1 6. —from a plurality of multiple inputs Decode at least one 200,405,662. 6. For each address, apply the patent scope. ^. ^ ^ With the corresponding address ::;:, there are logical state selection values, item set;, the corresponding address' forms a plurality of and Using a plurality of complementary N-logics and the complement d of a logical function: When evaluating mother-items and term sets, each complementary N-. Luo Fu second corresponds to the complementary ~ '" logic circuit evaluation. The edit circuit will correspond to a plurality of Pull one of the first points to a low level; Shuangshuang 1 is calling for the use of a plurality of complementary P-logic circuits, the complement of which and the logical function, and the set of u, ,, and items to evaluate the main complement. P-Logic Circuit Evaluation Point ::: Mutual? The logic circuit pulls one corresponding to the plurality of second evaluation points to a high level; when the evaluation of the N-logic circuit fails, one corresponding to the plurality of conductive elements is controlled by one corresponding to the first evaluation point, Pulling a corresponding second evaluation point to a low level; and using a logic gate to combine the second evaluation point to provide a decoding bit. 17 · The method as described in item 16 of the scope of application, further comprising: using a plurality of N-channel elements coupled in parallel between the corresponding first evaluation point and the reference point to implement each complementary N-logic circuit; An N-channel end element is provided between the reference point and the ground point and each ^ end element is controlled with a clock signal; at the same time, a plurality of P-channel elements are coupled in parallel between the corresponding second evaluation point and the source voltage to achieve each complementary P -A logic circuit; 18. The method according to item 16 of the scope of application, wherein pulling the corresponding second evaluation point to a low level includes at least: 1 Page 42 25? 200405662 6. Scope of patent application Reverse and buffer a clock signal and provide a reverse clock signal; meanwhile, the corresponding second evaluation point is driven by the reverse signal through the conducting element. 19. The method as described in item 16 of the scope of application, further comprising when a corresponding complementary N-logic circuit evaluation fails, saving a corresponding first evaluation point to be pulled to a high level to maintain activation of the corresponding conduction element. 2 0. The method according to item 16 of the scope of application, wherein the logic gate is merged. The second evaluation point includes at least the use of a reverse logic gate. Page 43