TH7204C3 - "Low-Density Parity-Check - Google Patents

Abstract

DC60 (18/08/54) Low-density parity check encoder and decoder for communication and telecommunication systems in accordance with IEEE802.16 standard. Encrypted with a block parity check feature with high encryption efficiency, decoding is based on the original principle of belief propagation algorithm BP that is complex in computation and Wasteful Memory resources are required, algorithms or lambda min algorithms with log-likelihood ratio and design number 1 check node processor (CNP). Nodes only, which is the reduction of the diffusion processing process. Trust Increasing the flexibility of decoding to enable decoding at any decoding rate (Flexible) and better performance in terms of hardware-level circuiting, which is a chip-based design. It has features to reduce the error rate (BER) to increase speed. Reduce the usage area and processing time. The low density parity check encoder and decoder for telecommunication and telecommunication systems in accordance with the IEEE802.16 standard is based on this invention. Encrypted with a block parity check feature with high encryption efficiency, decoding is based on the conventional principle of belief propagation algorithm (BP) with complex computation. And wasteful The memory resource is an algorithm or an algorithm (Lambda min) with the log probability ratio. (Log-likeihood) and designed only one check node (CNP) processing unit, which simplified the process of propagation. Trust Increasing the flexibility of decoding to enable decoding at any decoding rate (Flexible) and better performance in terms of hardware-level circuiting, which is a chip-based design. It has features to reduce the error rate (BER) to increase speed. Reduce the usage area and processing time:

Claims (1)

1. Low-Density Parity-Check (LDPC) encoder and decoder for communication and telecommunication systems complying with the IEEE802.16e standard containing i) the input port receives the data. From the signal splitter or demodulator (Demodulator) to the decoder, checks the density of the parity check, and receives the signal from the decoder when the first bit is sent to the decoder. ii) The output port sends the signal bits 0 and 1 from the decoder. Parity Check Parity Parity Check III) Variable Node Processor (VNP), processing the resulting data signal. Obtained by means of a technical pipeline and add R value to the counter. Each cycle of the loop where (R = R + 1) and the signal is sent to the sub-saffron network iv) the sub-saffer network. Serves to find the correct path of the signal transmission The data from the Variable Node Processor (VNP) to the Check Node Processor (CNP), the messages will be swapped and find the correct path of transmission. Information from the processor node VNP variable to the CNP check node processor to send the data signal to the CNP check node processor v) CNP check node processor (check nodes), perform processing and transmit. Signal data back to different variable processor nodes (VNP). Using the principle of lambda min (Lambda-min), which will then send Signal to Saffron network, and its characteristics are There is only one CNP check node processor.