TH5420B - A circuit system that is a combined series of bits - Google Patents

Abstract

A series of bit integrator circuits consisting of a series of bit mergers (12), a series recorder of the first bit (16), and a series recorder. of the second bit (22), the input signal is fed to the input. The signal output terminal of the second bit series recorder (22) is connected to the input of the second bit adder circuit (12). Delay (18) is connected to the signal output of the serial recorder. of the first bit (16) and is placed in a pass-through condition. a predetermined number of sample bits and delays, and emit a particular sample bit signal During the sample signal phase, the damper's output will be the input signal that has been merged, has a specified size and is trimmed as needed.

Claims (6)

1. An integrated circuit of a series of bits. To combine the bit's serial signals, consisting of The terminal end at the entrance of the signal For signal input A series of bits into Way of integration In order to combine the serial signal of the bit with one end of the signal input connected to the end. The input terminal of the said signal The second signal input terminal and the signal exit terminal. 1st series motion log with R number R class is an integer. The signal input terminal is connected. With the signal exit terminal of the aforementioned integration path, the signal exit terminal and the first serial motion recorder end terminal with N numbers, the N class is an integer. The signal input terminal is connected. With the exit terminal of the motion recorder's signal The first series. The signal exit terminal is connected. With the second signal inlet end of the inclusion path Together with such And the input terminal of the stroke signal Path for entry Which the protruding part of the stroke The end of the stroke signal input terminal of the motion recorder. The first and second series. Pauls in the section The filing corresponds to the displayed bit of the serial signal. Of the said bit And the number of poles in such protrusions is at least R + N poles per sample signal period and the delay path with the signal inlet connected to the terminal end. The exit of the signal of the serial motion recorder at One such To pass a bit-sample signal during a predetermined portion of the filing. And delay and give the signal output of the specified bitcoin signal For each interval of the sample signal that follows. Of the said part 2. The combined circuit of the bit series as described in Clause 1, where the path for entering the paused protrusions with the number of paused protrusions is equal to the number of The step, measured as an integer of the bit signal range, takes place between the inlet end of the path signal. Such a combination And the terminal end that is the solution of The signal of the aforementioned second series motion recorder 3. The integrating circuit of the bit series as described in Clause 2, where the inclusion path has a delay phase of one example bit signal interval at It is between the signal inlet end and its signal outlet end and the path to feed the power protrusion. Strokes, with the number of poles protrusions equal to the number of R + N + 1. 4. In conjunction, the method of joining together a series of bits in order to combine The bit series binary signal has the signal input terminal. One and the second And the terminal that is the exit of the signal The first bit series motion log with R steps (R is an integer) has the inlet end of the first bit. The coupling signal is connected to the exit terminal of the signal of the combined path. Together of the aforementioned bit series Will have the exit terminal of Signal, and there is a pulsation signal input terminal for input The first stroke signal to the signal sample of the bit series. Moving coherently through that stage The second bit serial motion recorder with N steps (N is an integer) has the signal input terminal. Connected to the output terminal of the signal recorder The first bit series movement has the terminal end of the coupling signal and the second signal inlet of the bundling path of the bit series. And there will be the end of the input terminal of the rhythm signal to enter the signal. The second stroke to the sample signal of a series of bits moving Consistently through its layers Bit-series alignment path with the inlet end of The signal is connected to the output terminal of the signal recorder. It moves in a series of the first bit and has a terminal end. The exit of the signal where the bit's serial signal is passed. Then will happen The deferred path will be determined. The conditional phase one passes a predetermined amount of signal. Bit, an example of a sample signal of a series of bits fed to the said delay path. And was conditionally set in the second step Delay and output the specified bit of the serial sample signal. Of the said bit Is the period of the sample signal after Where the above specified bit has occurred Example signal of a series of such bits 5. The integral part of Clause 4 also includes methods for entering intelligence at the first and at the Two such signals to the terminal end of the said rhythm signal The first and second rhythm signals are formed as part. Repeated paul filings, such protrusions include at least (R + N) poles per filing. 6. Part that is merged together Clause 5 also includes an aggregation path of another series of bits with one end of the signal input connected to the terminal. The exit of the signal of the bit series delay path. The signal output terminal is connected to the inlet end of the The first signal of the inclusion path and where the processed signal takes place and has the second signal inlet end and the way for feeding the bit's serial signal to the terminal end. Entrance Of the second signal of the integration path of the series Of the other one (6 claims, 3 pages, 3 pictures)