TH41410A - Methods and mechanisms for mapping invertible binary sequences to a 2/3 (1,K) encoded sequence of finite execution length with density bounds at the maximum transition point. - Google Patents

Abstract

DC60 (26/08/42) Methods and mechanisms for reducing high-turnover, unconstrained binary sequences in processes, communication systems, and storage units by inverting the position mapping of these sequences into a 2/3 rate constrained RLL(1, k) stream, thus approximating the true one-third of the duty cycle. That is, the normal binary position mapping into a high-turnover RLL coding sequence is either prevented from repetitive in nature or eliminated.

Claims (8)

1. The procedure performed by the processor for mapping an invertible binary sequence into a encoded sequence (RLL) of 2/3 (1,k) execution length bounded with maximum transition density is as follows: (a) The scope and storage of transition tables of the sequenced pairs, including the next state (n1n2n3) and the current RLL encoded three-bit symbol (c1c2c3) into the processor, where the sequenced pairs in each such table are indexed in the first table dimension according to their current state and in the second table dimension according to the vector (b1b2b3b4) of the predefined and current (b1b2) numbers of forward bit pairs (b3b4) from the binary sequence, where the current bit pair is a recognizable binary value (00,01,10,11), where each predefined number of forward bit pairs is selected from a set of recognizable binary values. and the value that does not take into account (xx) and the transition from one state to another which is limited by that any long sequence of three RLL encoded bits has a duty cycle of less than 50 percent and (b) the ability of such a processor to access a table that responds to the vector walk of bit pairs and retrieves a sequence of three RLL encoded bits from the table. 2. The method under claim 1 shall consist of the following steps: (c) defining the scope and maintaining a state-independent decoding table containing an account of binary bit pairs indexed by a vector constructed from the current RLL encoded three-bit vector and a predetermined number of RLL encoded three-bit vectors looking forward into such processor; and (d) making such processor access to such decoding table in response to a continuation of the RLL encoded three-bit vector and extracting the continuation of binary bit pairs from such table. 3. The method according to claim 2, in which the RLL (1, k) code limitation states, is chosen from the set consisting of (1, 9) and (1,13). 4. The method according to claim 1, in which the number of cycles is approximately one-third, and the RLL (1, k) constraint is still chosen from the set of (1, 9), (1,10) and (1,13). 5. The arrangement for producing an invertible binary sequence (RLL) encoded with a 2/3 (1, 9) execution rate limit and a dense bound at the maximum transition point, consists of the following components: a finite state machine (FSM) for producing the RLL encoded three-bit symbol (C1C2C3) as a first function of the current FSM state (S1S2S3) and a vector (b1b2b3b4) of the current (b1b2) and a predefined number of forward bit pairs (b3b4) from the binary sequence; and for producing the next processor internal machine state (n1n2n3) as a second function of the current FSM state and the binary sequence vector, where the current bit pairs are recognized binary values (00, 01,10,11), each predefined number of forward bit pairs is chosen from a set of The binary values that are recognized and the values that are ignored (xx), where the first and second functions are defined by a number of relationships that have Boolean algebraic values such as n1 = b1S3 + b1b2'b3'S1'S2 + S1S23 n2 = b1'S3 n3 = b2'S3 + 'S1'b1b2 C1 = 'S1 = 'S2 C2 = 'S1'S2'C3 C3 = 'S1S3 (b1 + 'b2) + 'S1'S2'S3b1b2'b3b4 6. Arrangement according to claim 5, which still consists of logic circuits that respond to the continuity of a three-bit vector encoded with RLL to extract the continuity of binary bit pairs, where the three-bit vector encoded with RLL is constructed from the current three RLL encoded bits (r1r2r3) and a predetermined number of three RLL encoded bits looking ahead (r4....r9). This logic circuit consists of: the first circuit for constructing the variables in the first Boolean equation (z1z2z3), the second circuit for constructing the variables in the second Boolean equation (U1U2.....U6), and the third circuit for bringing the binary bit pairs into a function for. The variables in the second Boolean equation, the first loop, are defined according to a number of relations that have values according to the Boolean equation, such that Z1 = '(r1+r2+r3), Z2 = '(r4+r5+r6), Z3 = '(r7+r8+r9), and the second loop is defined according to a number of relations that have values according to the Boolean equation, such that U1 = r1, U2 = ('Z1-'Z2) r3 + 'Z1Z2'Z3, U3 = 'Z1Z2, U4 = Z2Z3 + 'Z1Z2'r3, U5 = O, U6 = Z2Z3r3. 7. The arrangement for producing an invertible binary position map (RLL) encoded sequence (RLL) with a 2/3 (1,13) execution rate limit and maximum transition density is as follows: a finite state machine (FSM) for producing the RLL encoded three-bit symbol (c1c2c3) as the first function of the current number of FSM states (s1s2s3) and a vector (b1b2b3b4b5b6) of predefined and current (b1b2) numbers of forward binary sequence bit pairs (b3b4b5b6), and for producing the next processor state (n1n2n3) as the second function of the current FSM state and the binary sequence vector, where each current bit pair is a recognizable binary value (00, 01,10,11), and each predefined number of forward bit pairs is selected from a set of recognizable binary values. and the value that is ignored (xx), where the first and second functions are limited by a number of relationships that have values according to the Boolean equation, such that n1 = (S1S2) + (S3b1) + (S1b1b2'b3) + Cs1b1b2'b4b5b6) n2 = ('S2b1) + (S1S2b1'b2) n3 = (S1b2) + ('S'b1'b2) + (S1S2b1'b2) C1 = ('S1S2) C2 = ('S1'S2'C3) C3 = ('S1S3) ('b1+'b2) + ('S1'S3b1b2'b3b4) 8. The production material consists of machine-readable memory containing a processor that executes a number of control program steps for rendering an invertible binary sequence (RLL) coded sequence of finite length, executed at a 2/3 (1,k) rate with a density bound at the maximum transition point. Such control program steps shall consist of (a) a control program step for scoping and storing a table of transitions of the sequenced pairs and the next transition (n1n2n3) and the current RLL encoded three-bit symbol (C1C2C3) in the processor, where each sequenced pair in such table It is indexed in the first tabular dimension according to its subsequent state and in the second tabular dimension according to the vector (b1b2b3b4) of the current predefined number (b1b2) of the forward bit pair (b3b4) from the binary sequence, where the current bit pair is a recognizable binary value (00, 01, 10, 11). Each predefined number of the forward bit pair is selected from a set of both recognizable and indifferent binary values (xx), where the transition from one state to another is limited by the fact that any long sequence of the three RLL encoded bits exhibits less than 50 percent duty cycles, and (b) the program control procedure that executes for the processor to access the table that responds to the bit pair vector walk and for retrieving the sequence of the three RLL encoded bits from that table.