TH40197A - Methods and equipment for retrieving video data across multiple standards. - Google Patents

Abstract

DC60 This invention relates to the retrieval of multi-standard video data using a decoder with register 201 containing 24 cells to store 3 x 8 bits of data. Each of the three bytes is connected to a logic device to compare the portion in the cell with a given start code, at which point the start of register 202 is byte 3, followed by byte 2 and byte 1. In addition, a second 8-bit register 202 is connected in parallel with register 201. The portion of byte 3 is fed to the Hamming (8/4) decoder 203, and the portion of byte 3 is fed to the Hamming (8/4) decoder 204. The 4-bit output of each decoder is fed to the 4-bit portion of register 202, respectively. This invention relates to... The multi-standard video data retrieval uses a decoder with register 201, containing 24 cells to store 3 x 8 bits of data. Each of the three bytes is contiguous to a logic device to compare the portion in the cell with a given start code. The starting point of register 202 is byte 3, followed by byte 2 and byte 1. Additionally, a second 8-bit register, 202, is connected in parallel with register 201. The portion of byte 3 is fed to the Hamming (8/4) decoder 203, and the portion of byte 2 is fed to the Hamming (8/4) decoder 204. The 4-bit output of each decoder is fed to the designated 4-bit portion of register 202, respectively.

Claims (10)

1. A multi-standard video data retrieval method where, as defined by the characteristics, the incoming data stream (TTD_ACT) is fed into memory location (201) where it is searched in parallel for different start codes (SCVPS1, SCVPS2, SCWSS1, SCWSS2, SCWSS3, SCCC, SCGEM) on the same data containing different frame codes of different services when the actual video pair service is not specified and the start codes searched are changeable by morphology. 2. The method specified in claim paragraph 7, whereby the decoder can be connected or disconnected by the microprocessor via the junction signal (DA_ENABLE). 3. The method specified in Claim 1, in which the clock frequency of the decoder is matched to the frequency of the various source codes. 4. The method specified in Claim 1, in which the Select Service Block determines the type of frame code to search based on the line pair number (LINE_NO) of the input signal, the standard applied (NORM625) of that input signal, and the valid code (L16VPS) in that specific line pair of the input signal. 5. The method specified in Claim 1, whereby within the operating range of the service-specific timing signal (SW) generated by the search window generator from a horizontal sync signal (HSYNC) of up to 3 bytes, is scanned for the appropriate frame code. 6. The method specified in claim 5 shall apply 3 bytes to the frame code of a pair containing the first signal (WSS) with 24 elements at a frequency of 5 MHz. In the case of a pair containing the second signal (VPS), only 2 bytes shall be compared to the two-byte source code (VPSSC1, VPSSC2) at a frequency of 5 MHz. In the case of a pair containing the third signal (CC, GEM), only 1 byte shall be compared simultaneously to both source codes (SCCC, SCGEM) at a frequency of 1007 kHz. In the case of a pair containing the forward signal (WST), only one bit shall be used to compare to the frame code at a frequency of 6.9375 MHz. When the source code is detected during the active search window (SW) by the trigger signal (VSD), data shall be sent to the buffer (VBI) which will be handled by the output control block. 7. The method specified in claim 6, whereby in the case of a pair containing a second signal (VPS) in addition to the trigger signal (VSD), another signal (VPSD) is sent to the microprocessor register to indicate receipt of data on some pairs. 8. The method specified in Claim 5 or 6, in which, in the case of a pair containing a fourth signal (WST), two bytes following the WST frame code are decoded during the lookup and the result is inserted in parallel into the second memory (202), and when the WST frame code is detected by the data, it is transferred to the buffer (VBI) via this memory (202). 9. Multistandard video data retrieval device, which includes: - a path to provide the source code (206, 207, 208) - a path to collect the incoming data stream (201) - a path to compare the source code with the incoming data stream. 10. Equipment as specified in claim 9, which includes additional means to decode (203, 204) and store (202) such incoming data streams.