TH39049B - Energy-balanced ink nozzle design - Google Patents

Abstract

The DC60 (08/03/45) narrow inkjet printhead (100A, 100B) features an efficient FET propulsion circuit (85), which is configured to compensate for the parasitic resistance of the power traces ( 86a, 86b, 86c, 86d, 181) This spray printhead also includes a ground bus (181), which overlaps the active region of the narrow spray printhead FET propulsion circuit. (100A, 100B), which has an efficient FET thrust circuit (85), which is configured to compensate for the parasitic resistance of the power traces (86a, 86b, 86c, 86d, 181). This also includes the ground bus section (181), which overlaps the active region of the FET drive circuit.

Claims (1)

Disclaimer (all) which will not appear on the advertisement page: 1. Ink jet print head which consists of Print head strapping Including the thin film layer Column-shaped array Of the ink droplet generator Restricted in Chop the said printhead strip and spread it along the longitudinal axis L each ink drop generator with the fuser resistor. Which has a valuable resistance At least 100 ohms pillar-shaped sequences of the FET circuit built into the substrate. The printhead is and is connected to the ink droplet generator respectively where the FET circuit includes an individual actuation region comprising the drain region, the source region and the gate circuit. Each FET circuit has less open resistance (250,000 ohm-2 μm) / A, where A is the area of the FET in 2 micrometers. It is connected to the blotter generator and the said FET thrusters and the said FET thrusters configured to compensate for variations in resistance. Parasites delivered by the said power trace 2. The print head as mentioned in claim 1, provided that the oxide layer of the said gate has a thickness that is Maximum value 800 angstroms 3. Print head as stated in claim 1 where each FET circuit has gate length less than 4 micrometers 4. Print head as stated in claim 1 where FET circuit Each circuit has a resistance value. When turned on at a maximum of 16 ohms. 5. Printhead as indicated in claim 1, where each FET circuit has a resistance. 14 ohms max. 6. The printhead as indicated in claim 1, where the pillar-like array of the FET circuit is placed in the FET region, the width at the right angles to the longitudinal axis. L with a maximum such width of 350 micrometers 7. The print head is stated in claim 1 where the pillar-like array of the FET circuit is placed in the FET region, which has Width at right angles to the longitudinal axis L with a maximum of 250 μm. 8. The print head as stated in claim 1, provided that the tracer includes the ground bus part. This will overlap the column-shaped row of the FET drive circuit 9. The print head is stated in claim 8, provided that the ground bus has a transverse width. To the longitudinal reference axis L, which is proportional to the longitudinal reference axis L 1 0. The print head is indicated in claim 1 where the column-shaped array is Each row of the blotter generator is organized into the primary group M and by the trace. Such power will include the primary selection trace M connected sequentially to the aforementioned primary group M 1 1. The printhead as stated in claim 10, whereby the aforementioned printhead strip. Will include section A longitudinal end where M is the number of pairs and where M / 2 of the primal selection mark M is connected to the binder plate. Electrically at one such end and where the other M / 2 of the primal selection notch M is connected to Binder sheet The other end of the electrical term 1 2. The printhead as stated in claim 11, where M is four 1. 3. The printhead as stated in claim 10, whereby the primal selection M It is placed over the pillar-shaped array of the FET 1 drive circuit. 4. The print head is indicated in claim 1, with the blotter generator spaced. At least 1/600 inch apart along the longitudinal reference axis L 1 5. The printhead as stated in claim 14 where the blotter generators are spaced 1/300-inch apart. Longitudinal reference axis L 1 6. The print head is indicated in claim 1 where the resistor resistance of the carrier The heat is at least 120 ohms 1 7. Print head as stated in claim 1 where the resistor resistance of the carrier The heat will be at least 130 ohms 1 8. The printhead is stated in claim 1 where the corresponding activation resistance of the said FET circuit is selected to compensate for the variation in parasitic resistance. Sent The tracing of the aforementioned power 1 9. The print head as stated in claim 18 where each FET circuit size is Select to set the resistance when activated. 2 0. The print head is stated in claim 18 where each FET circuit includes Drain electrodes Contact drain The drain electrode is connected to the area of the drain. Source electrode Source contact Where the source electrode is connected to the said source region electrically and where such drain region is configured to set the open resistance of each FET circuit to compensate for the variation in Resistance to transmitted parasites Give the surrounding as follows 2 1. The print head is stated in claim 20 where the area of the drain will consist of: Each area of the long drain Including parts that are not in constant contact with It is selected to set resistance when it is activated.