TH31441A - Programmable crystal oscillator - Google Patents

Abstract

DC60 (27/03/41) A programmable crystal oscillator is provided with memory for storing frequency-determining parameters. Typically, one of these parameters is used to program a variable capacitive load circuit attached to the crystal to adjust the source frequency of the crystal. Additional parameters are used to program the output frequency of the attached phase-locked loop circuit to receive the variable source frequency. The parameters can also be used to divide the output frequency of the phase-locked loop circuit to feed a specified output frequency. The oscillator can be manufactured as a general-purpose programmable crystal oscillator regardless of the output frequency and then rapidly programmed to produce the customer-specified output frequency with high accuracy. The programmable crystal oscillator is provided with memory for storing frequency-determining parameters. Typically, one of these parameters is used to program a variable capacitive load circuit attached to the crystal to adjust the source frequency of the crystal. Additional parameters are used to program the output frequency of the attached phase-locked loop circuit to receive the variable source frequency. A parameterized source can still be used to divide the output frequency of a phase-locked loop circuit to provide a specified output frequency. Oscillators can be manufactured in the form of general-purpose programmable crystal oscillators regardless of the output frequency, and then rapidly programmed to produce the customer-specified output frequency with high accuracy.

Claims (26)

1. A timing circuit consisting of the following components: a crystal for generating the source frequency; a programmable load circuit coupled to the crystal; an oscillator circuit coupled to receive the source frequency; a frequency multiplier circuit coupled to the oscillator circuit to receive the source frequency; and a programming circuit configured to feed the first program data to the programmable load circuit to adjust the source frequency, and then feed the second program data to the frequency multiplier circuit, whereby the frequency multiplier circuit outputs a frequency equal to the product of the adjusted source frequency and the multiplier factor specified by the second program data. 2. The timing circuit under claim 1, whereby the programmable load circuit is a programmable capacitive load circuit. 3. A timing circuit under claim 2, in which the source frequency is fed through a crystal-encrusted source frequency transmission line, and a programmable capacitive load circuit consisting of capacitors, one of which is selected and connected to the source frequency transmission line. 4. The timing circuit under claim 3, which is a programmable capacitive load circuit, still consists of switching elements, each with a first terminal connected to the source frequency transmission line and a second terminal connected to one of the corresponding capacitors from among the said capacitors. 5. The timing circuit under claim 4, which is programmed to generate output signals based on the programmed information stored within it, is fed to a programmable capacitive load circuit to activate one of the selected switching elements, thereby connecting a corresponding capacitor from the group of capacitors to the source frequency transmission line. 6. The timing circuit according to claim 4, in which each of the switching elements consists of a MOS transistor. 7. The timing circuit under claim 1, which includes a frequency multiplier circuit containing a phase-locked loop. 8. The timing circuit according to claim 1, where the information in the second program consists of the first parameter P and the second parameter Q, where the output frequency (F out) and the adjusted source frequency (F adj) satisfy the condition (formula). 9. The timing circuit according to claim 7, where the frequency multiplier loop circuit consists of a first divider circuit to divide the source frequency, adjusted by the first parameter of the data in the second programming, to generate the first frequency; a second divider circuit integrated into the phase-locked loop to divide the output frequency by the second parameter of the data in the second programming, to generate the second frequency; and a detector integrated into the phase-locked loop and coupled to receive the first and second frequencies. The detector outputs a control signal in response to the first and second frequencies to control the generation of the output frequency. 10. The timing circuit pursuant to claim 9, which still consists of a third divider circuit, which is combined with the output of the aforementioned phase-locked loop circuit and the aforementioned programming circuit for dividing the output frequency by the third parameter of the data in the second programming circuit stored in the aforementioned programming circuit. 11. The timing circuit under claim 7, where the adjusted source frequency is fed to the divider circuit to generate a phase-locked loop frequency of less than 200 kHz. 12. A timing circuit pursuant to claim 11, where the loop frequency is within the range of 32 kHz to 50 kHz. 13. The timing circuit under claim 11, where the loop frequency is within the range of 42.395 kHz to 43.059 kHz. 14. The timing circuit under claim 9, where the detector outputs the control signal based on the phase difference between the first and second frequencies, and the phase-locked loop circuit still consists of a charge pump circuit that receives the control signal and outputs a DC signal in response, a filter loop, and a voltage-controlled oscillator coupled to the charge pump through the filter loop, where the voltage-controlled oscillator generates the output frequency under the control of the DC signal. 15. The timing circuit under claim 1, which still includes a dedicated external programming terminal for inputting the first and second programming data into the programmable read-only memory integrated into the programming circuit. 16. A programmable timing circuit consisting of the following components: a crystal; an oscillator circuit attached to the crystal to excite it and generate the source frequency; a capacitive load circuit attached to the crystal and programmed to have the desired load capacitance in order to selectively adjust the source frequency; and a phase-locked loop circuit attached to the oscillator circuit, which generates an output frequency as a product of the adjusted source frequency and a multiplier factor. 17. A programmable timer circuit pursuant to claim 16, which still comprises memory, is coupled with the aforementioned phase-locked loop circuit and with the aforementioned programmable capacitive load circuit for storing program data, which has a first parameter for programming the capacitive load circuit to the required load capacitance and a second parameter for programming the phase-locked loop circuit to the specified multiplication factor. 18. A programmable timer circuit in accordance with claim 17, whose memory shall consist of a PROM. 19. A programmable timer circuit pursuant to claim 17, in which the crystal is coupled to the oscillator circuit by the input line, shall have the following components: capacitors and switching elements, each with its first terminal coupled to one of the corresponding capacitors from among them, and its second terminal coupled to the second input line, and a memory unit that inputs the first parameter as a signal to trigger one of the selected switching elements, which in turn couples one of the corresponding capacitors from among them to the second input line. 20. A programmable timer circuit in accordance with claim 19, in which each of the switching elements consists of a MOS transistor. 21. A programmable timer circuit pursuant to claim 17, which continues to include a specially designed programming terminal that accepts external input of such programming data for storage in the said memory unit. 22. A programmable crystal oscillator with the following components: a crystal with a coupled source frequency; an oscillator circuit; an input line connecting the crystal to the oscillator circuit; a capacitive load coupled to the programmable input line to adjust the source frequency according to the load parameters; a phase-locked loop coupled to receive the adjusted source frequency and generate a loop frequency in response, where the phase-locked loop is multiplied by the loop frequency parameter to generate the desired output frequency; and a programming circuit coupled to the programmable capacitive load circuit and the phase-locked loop, respectively. The programming circuit stores the frequency and load parameters for programming the capacitive load circuit and the phase-locked loop circuit, respectively. 23. A programmable crystal oscillator under claim 22, which is an industry-standard clock crystal with a true source frequency of 32.768 kHz. 24. The timing circuit under claim 1 continues to consist of a primary PROM for storing indication data, a programming terminal for programming the primary PROM with such indication data, and a primary output terminal for reading such indication data from the primary PROM. 25. The timing circuit under claim 24 still consists of a second PROM programmed with the data from the first and second programming cycles fed through the programmer terminal, and a second output terminal for transmitting the output frequency and clock pulse signal to time the indication data into the first PROM and time the data from the first and second programming cycles into the second PROM. 26. The timing circuit as per claim 25, which still includes a second input connector for receiving the clock signal to read the aforementioned indication data from the first PROM and output it to the first output connector (Clause 26, page 6, figure 4).