TH24074B - Clock mapping in independent networks - Google Patents

Abstract

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Claims (80)

1. A clock rate matching device for independent networks is used in radiotelephone networks and has bits provided in the ISDN frame as input, transmitted at clock rate one. The device consists of a path for providing the second clock rate, a path for determining the clock state offset code based on the difference between the first and second clock rates, and a path that responds to the determination path to instruct the receiver within the radiotelephone network to tune to the first clock rate based on the clock state offset code transmitted to the receiver on the two ISDN frames. 2. Transmitter for clock rate matching between independent networks. This transmitter is used in radiotelephone networks and has at least one network information bit and at least one data bit as input, transmitted at the first clock rate. The transmitter consists of: a path for using a second clock rate; a path for accepting a minimum number of network information bits and at least one data bit predetermined and transmitted at the first clock rate; a path for determining the rate differential between the first and second clock rates; a path responding to the determination path for setting at least one network information bit to a predetermined value to indicate the selected clock offset; and a path for transmitting at least one network information bit representing the selected clock offset to instruct the receiver operating at the second clock rate to adjust itself to the first clock rate. 3. The transmitter pursuant to claim 2, whereby the acceptance method shall also include a buffering method for at least the said predetermined number of network information bits and at least the said predetermined number of data bits. 4. The transmitter pursuant to claim 3, whereby the method for such determination also includes a method for determining the difference between the rate at which the network information is transcribed (at least a predetermined amount) and the data is transcribed (at least a predetermined amount) into the buffer path, and the rate at which the network information is transcribed (at least a predetermined amount) and the data is transcribed (at least a predetermined amount) out of the buffer path. 5. The transmitter pursuant to claim 4, whereby the method for such determination is further comprised of a method for providing a lower threshold for the rate difference. 6. The transmitter pursuant to claim 4, whereby the method for such determination is further comprised of a method for providing an upper threshold for rate differential changes. 7. The transmitter, according to claim 2, whereby the paths for setting at least one network information bit to a predefined value are further comprised of: a path for setting at least one network information bit to a predefined value representing the first clock compensation state when the found rate difference is less than the lower threshold of the found rate difference; a path for setting at least one network information bit to a predefined value representing the second clock compensation state when the found rate difference is less than the upper threshold of the found rate difference and greater than the lower threshold of the found rate difference; and a path for setting at least one network information bit to a predefined value representing the third clock compensation state when the found rate difference is greater than the upper threshold of the found rate difference. 8. The transmitter under claim 7, whereby the transmission path to instruct the receiver operating at the second clock rate to adjust itself to the first clock rate, shall also include a transmission path for the first clock rate offset state instructing the receiver to subtract one bit from a predetermined set of data bits, and a transmission path for the third clock rate offset state instructing the receiver to add at least one bit to a predetermined set of data bits. 9. The transmitter pursuant to claim 2, whereby the path for such setup includes an additional path for pre-correction of at least one bit of network information. 10. Clock Rate Matching Receiver Between Independent Networks. The receiver is used in the source network and connected to the destination network operating at clock rate one. The receiver has at least one serially transmitted data frame as input. This data frame contains at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at clock rate two. The predetermined number of network information bits contains at least one bit representing at least one clock offset state. The receiver contains paths for receiving at least one data frame containing at least the predetermined number of network information bits and at least a predetermined number of data bits transmitted at clock rate two; a path that responds to the receiving predetermined number of network information bits for determining the clock offset state; a path that responds to the determination path for swapping at least one of the received predetermined data bits; and a path that responds to the swap path for adjusting the receiving clock rate two to match the clock rate one. 11. The receiver pursuant to claim 10, whereby the path for determining the clock compensation state is further comprised of paths for determining at least one state of the first, second, and third clock compensation states. 12. The receiver, pursuant to claim 11, whereby the path for swapping the said predetermined number of data bits by at least one bit shall also include a path that responds to such path for determining the result of determining the first clock offset state for subtracting one bit from the said predetermined number of data bits and a path that responds to such path for determining the result of determining the third clock offset state for adding the said predetermined number of data bits by at least one bit. 13. A data link in a radio telephony network uses one transmitter for clock rate matching between independent networks. The transmitter has at least a network information bit and at least a data bit as input, transmitted at the first clock rate. The data link consists of a path for providing a second signal at the second clock rate; a path for accepting at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at the first clock rate; a path for determining the rate difference between the first clock rate and the chosen clock rate; and a path for transmitting at least one such network information bit representing the chosen clock offset state to instruct the receiver operating at the second clock rate to adjust itself to the first clock rate. 14. Data link pursuant to claim 13, whereby the path for such acceptance is further comprised of a path for buffering at least one bit of network information, a predefined number of bits of data, and at least one bit of data, a predefined number of bits. 15. Data Interconnection, pursuant to claim 14, whereby the method for such determination is further comprised of a method for determining the difference between the rate at which a minimum predetermined number of network information bits and a minimum predetermined number of data bits enter the buffer path and the rate at which a minimum predetermined number of network information bits and a minimum predetermined number of data bits exit the buffer path. 16. Data linkage, pursuant to claim 15, whereby the method for such determination is further comprised of a method for providing a threshold for the lower rate difference. 17. Data linkage, pursuant to claim 15, whereby the method for such determination is further comprised of a method for providing a threshold for the above rate difference. 18. Data Interconnection, pursuant to claim 13, whereby the paths for setting at least one network information bit to a predefined value are further comprised of: a path for setting at least one network information bit to a predefined value representing the first clock offset state when the obtained rate difference is less than the threshold of the lower rate difference; a path for setting at least one network information bit to a predefined value representing the second clock offset state when the obtained rate difference is less than the threshold of the upper rate difference and greater than the threshold of the lower rate difference; and a path for setting at least one network information bit to a predefined value representing the third clock offset state when the obtained rate difference is greater than the threshold of the upper rate difference. 19. Data linkage, pursuant to claim 18, whereby the path for transmitting such a mechanism to instruct the receiver to operate at the second clock rate and adjust itself to the first clock rate, is further comprised of a path for transmitting such a mechanism for transmitting the first clock rate offset state which instructs the receiver to subtract one data bit from a predefined set of data bits, and a path for transmitting such a mechanism for transmitting the third clock rate offset state which instructs the receiver to add at least one bit to a predefined set of data bits. 20. Data linker, pursuant to claim 13, whereby the path for such setup is further supplemented with a path for pre-correction of at least one bit of network information. 21. Interconnect. In a source network using a clock-rate-matched receiver, the receiver has at least one serially transmitted data frame as input. This data frame contains at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at the second clock rate. The predetermined number of network information bits contains at least one bit representing at least one clock offset state. The interconnect consists of a path for receiving at least one data frame containing at least the predetermined number of network information bits and at least a predetermined number of data bits transmitted at the second clock rate; a path that responds to the received predetermined number of network information bits for determining the clock offset state; a path that responds to the determination path for switching at least one of the received predetermined data bits to the first clock rate; and a path that responds to the switching path for adjusting the second clock rate to match the first clock rate. 22. Data link pursuant to claim 21, whereby the path for determining the clock compensation state is further comprised of paths for determining at least one state of the first, second, and third clock compensation states. 23. Data link, pursuant to claim 22, where the path for swapping the said predetermined number of data bits by at least one bit shall also include a path that responds to such path for determining the result of the first clock offset state for subtracting one bit from the said predetermined number of data bits, and a path that responds to such path for determining the result of the third clock offset state for adding at least one bit from the said predetermined number of data bits. 24. A communication system that uses at least two first and second interconnects for clock rate matching between independent networks. The first interconnect uses a transmitter that has at least a certain number of network information bits and at least a certain number of data bits transmitted at the first clock rate as input. The second interconnect is connected to the receiving network that has a third clock rate. The communication system consists of: a path at the first interconnect for the second clock signal at the second clock rate; a path at the first interconnect for accepting at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at the said first clock rate; a path at the first interconnect that responds to the path for such acceptance; a path for setting at least one network information bit to a predetermined value to represent the selected clock offset state; a path at the first interconnect for sending at least one such network information bit representing the selected clock offset state to the second interconnect; and a path at the second interconnect. For receiving at least one such network information bit representing the selected clock offset state, the path at the second interconnect and in response to receiving at least one such network information bit for determining the selected clock offset state, and the path at the second interconnect and in response to the path for determining such state, for swapping the received data bit by an integer multiple of the data bit to match the second clock rate with the third clock rate. 25. Transmitter for Clock Rate Matching Between ASSA Networks. The transmitter is used in the source network and has at least a few state bits, network information bits, and data bits transmitted at the first clock rate as input. The transmitter consists of: a path for providing a second clock signal with a second clock rate; a path for accepting at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the first clock rate; a path for determining the rate difference between the aforementioned first clock rate and the aforementioned second clock rate; a path responding to the aforementioned determination path for setting at least one network information bit to a predetermined value to represent the selected clock offset state; a path for adjusting the aforementioned predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits into at least two groups representing data transfer frames; and a path using at least one remaining network information bit from the first data transfer frame for pre-correcting at least one such network information bit of the aforementioned first data transfer frame. The path that responds to the path for such a set, for swapping a predetermined number of data bits of the second data transfer frame with at least one data bit, and the path for transmitting at least the first and second data transfer frames. 26. Transmitter, pursuant to claim 25, whereby the means of acceptance shall also include a means of buffering at least the said predetermined number of state bits, the said predetermined number of network information bits and at least the said predetermined number of data bits. 27. The transmitter, according to claim 26, whereby the method for such determination also includes a method for determining the difference between the rate at which the minimum predefined state bits, the minimum predefined network information bits, and the minimum predefined data bits enter the buffer path and the rate at which the minimum predefined state bits, the minimum predefined network information bits, and the minimum predefined data bits exit the buffer path. 28. The transmitter pursuant to claim 27, whereby the method for such determination is further comprised of a method for providing a threshold for changing the rate difference. 29. The transmitter pursuant to claim 27, whereby the method for such determination is further comprised of a method for providing an upper threshold change of the rate difference. 30. The transmitter, according to claim 25, whereby the paths for setting at least one network information bit to the predefined value are further comprised of: a path for setting at least one network information bit to the predefined value representing the first clock compensation state when the obtained rate difference is less than the lower threshold of the obtained rate difference; a path for setting at least one network information bit to the predefined value representing the second clock compensation state when the obtained rate difference is less than the upper threshold of the obtained rate difference and greater than the lower threshold of the obtained rate difference; and a path for setting at least one network information bit to the predefined value representing the third clock compensation state when the obtained rate difference is greater than the upper threshold of the obtained rate difference. 31. Transmitter. Under claim 30, whereby the path for changing the said predetermined number of data bits by at least one bit shall also include a path that responds to the first clock offset for subtracting one bit from the said predetermined number of data bits and a path that responds to the third clock offset for adding at least one bit from the said predetermined number of data bits. 32. The transmitter, pursuant to claim 25, shall also include a pathway that uses at least one state bit from at least one frame of the first and second data transfer frames for pre-determined error correction; such predetermined number of state bits shall be used. 33. Transmitter, pursuant to claim 25, whereby the path for such setup also includes a path for pre-correcting at least one bit of network information error. 34. Receiver for Clock Rate Matching Between Independent Networks. The receiver is used in the source network and connected to the destination network operating at clock rate one. The receiver has at least one serially transmitted data frame as input. This data frame contains at least a predefined number of state bits, at least a predefined number of network information bits, and at least a predefined number of data bits transmitted at clock rate two. The predefined number of network information bits contains at least one bit representing at least one clock offset state and at least one bit representing at least one error correction prefix of the bits representing such predefined clock offset state. The receiver contains pathways for receiving at least the first and second data frames, each containing at least a predefined number of state bits, at least a predefined number of network information bits, and at least a predefined number of data bits transmitted at clock rate two. A pathway responds to the reception of these predefined number of network information bits for decoding the prefix error correction of at least one of the network information bits. The received bit represents at least one clock compensation state to determine that clock compensation state. The path responds to the decoding path for switching at least one predetermined data bit of the second transfer frame, and the path responds to the switching path for matching the second clock rate to the first clock rate. 35. The receiver under claim 34, whereby the path for determining the clock compensation state is further comprised of a path for determining at least one state of the first, second and third clock compensation states. 36. The receiver under claim 35, whereby the path for swapping the predetermined number of bits by at least one bit, shall also include a path that responds to the path for determining the result of the first clock offset state for subtracting one bit from the predetermined number of bits, and a path that responds to the path for determining the result of the third clock offset state for adding at least one bit from the predetermined number of bits. 37. The interconnect in the source network uses a transmitter for clock rate matching between independent networks. The transmitter is used in the source network and has at least a state bit, a network information bit, and a data bit transmitted at the first clock rate as input. The interconnect consists of a path for providing a second clock signal with the second clock rate; a path for accepting at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the first clock rate; a path for determining the rate difference between the said first clock rate and the said second clock rate; and a path that responds to the path for determining the rate difference to set at least one network information bit to a predetermined value to represent the selected clock offset state. A path for adjusting at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits into at least two groups representing a data transfer frame; a path that uses at least one remaining information bit or bit from the first data transfer frame for pre-correction of at least one network information bit at the edge of the first data transfer frame; a path that responds to the such setting path for swapping a predetermined number of data bits of the second data transfer frame with at least one data bit; and a path for transmitting at least the first and second data transfer frames. 38. The data interface according to claim 37, whereby the means of acceptance shall also include a means of buffering at least the aforementioned predetermined number of state bits, the aforementioned predetermined number of network information bits, and at least the aforementioned predetermined number of data bits. 39. The data interface according to claim 38, whereby the method for determining such a method is further comprised of a method for determining the difference between the rate at which a minimum predefined number of state bits, a minimum predefined number of network information bits, and a minimum predefined number of data bits enter the buffer path, and the rate at which a minimum predefined number of state bits, a minimum predefined number of network information bits, and a minimum predefined number of data bits exit the buffer path. 40. The data link pursuant to claim 39, whereby the method for such determination is further comprised of a method for providing a lower threshold for rate differences. 41. The data link under claim 39, whereby the method for determining such a link is further comprised of a method for providing an upper threshold for rate differences. 42. The interconnection device under claim 37, whereby the paths for setting at least one network information bit to a predefined value are further comprised of: a path for setting at least one network information bit to a predefined value representing the first clock offset state when the resulting rate difference is less than the lower threshold of the rate difference; a path for setting at least one network information bit to a predefined value representing the second clock offset state when the resulting rate difference is less than the upper threshold of the rate difference and greater than the lower threshold of the rate difference; and a path for setting at least one network information bit to a predefined value representing the third clock offset state when the resulting rate difference is greater than the upper threshold of the rate difference. 43. The interconnection under claim 42, whereby such a path for swapping the said predetermined number of bits by at least one bit, shall also include a path responding to the first clock offset state, for subtracting one bit from the said predetermined number of bits, and a path responding to the third clock offset state for adding at least one bit to the said predetermined number of bits. 44. The linker under claim 37, which is further comprised of a path that uses at least one state bit from at least one frame of the first and second such transfer frames for the purpose of pre-correcting the error of such predetermined number of state bits. 45. A data link pursuant to claim 37, whereby the path for such set also includes a path for pre-correcting at least one bit of network information error. 46. A data link in a source network that uses a receiver for clock-rate matching between independent networks. The receiver is used in the source network and connected to a destination network with a first clock rate. The receiver has at least one serially transmitted data frame as input. This data frame contains at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the second clock rate. The predetermined number of network information bits contains at least one bit representing at least one clock offset state and at least one bit representing at least one pre-correction error bit representing at least one such bit representing at least one such clock offset state. The data link contains at least two paths for the first and second data frames, each containing at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the second clock rate. The path responds to the reception of the predetermined number of network information bits. For decoding the aforementioned error correction advance of at least one received network information bit representing at least one clock offset state to determine the clock offset state, the path responding to the decoding path for switching at least one predefined data bit of the second data transfer frame, and the path responding to the decoding path for switching at least one predefined data bit of the second data transfer frame, and the path responding to the switching path, for matching the second clock rate to the first clock rate. 47. The data link pursuant to claim 46, whereby the path for determining the clock compensation state is further comprised of a path for determining at least one state of the first, second, and third clock compensation states. 48. The interconnection path under claim 47, whereby such path for swapping the said predetermined number of bits by at least one bit, shall also include a path responding to such path for determining the result of the first clock offset state for subtracting one bit from the said predetermined number of bits, and a path responding to such path for determining the result of the third clock offset state for adding at least one bit from the said predetermined number of bits. 49. A communication system that uses at least two first and second interconnects for clock rate matching between independent networks. The first interconnect uses a transmitter which has at least a state bit, at least a network information bit, and at least a data bit as input transmitted at the first clock rate. The second interconnect is connected to the receiving network which has a third clock rate. The communication system consists of: a path at the first interconnect for providing the second clock signal at the second clock rate; a path at the first interconnect for accepting at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the aforementioned first clock rate; a path at the first interconnect for determining the rate difference between the first and second clock rates; a path at the first interconnect and in response to the path for such determination; for setting at least one network information bit to a predetermined value to represent the selected clock offset state; and a path at the first interconnect. For adjusting at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits, to form at least two groups representing the data transfer frame, the path at the first interconnect uses at least one remaining network information bit from the first data transfer frame for pre-correcting at least one network information bit of the first data transfer frame. The path at the first interconnect responds to the path for such correction for swapping a predetermined number of data bits of the second data transfer frame with at least one data bit. The path at the first interconnect transmits at least the first and second data transfer frames. The path at the second interconnect receives at least the first and second data transfer frames, each containing at least a predetermined number of state bits, at least a predetermined number of network information bits, and at least a predetermined number of data bits transmitted at the second clock rate. The path at the second interconnect responds to the receipt of such predetermined number of network information bits for decoding such pre-correcting of the network information bits. At least one received bit representing at least one clock compensation state determines that clock compensation state. The path at the second interconnect responds to the decoding path for switching at least one bit of the predetermined number of data bits of the second data transfer frame, and the path at the second interconnect responds to the switching path for matching the second clock rate with the third clock rate. 50. Methods for Matching Clock Rates Between Independent Networks in a Data Link: The data link has a transmitter that has at least a certain number of network information bits and at least a certain number of data bits transmitted at the first clock rate as input. The method consists of the following steps: providing a second clock signal with a second clock rate; accepting at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at the said first clock rate; determining the rate difference between the said first and second clock rates; setting, in response to this determination step, at least one network information bit is set to a predetermined value to represent the selected clock offset state; and transmitting at least one of these network information bits representing the selected clock offset state to instruct the receiver operating at the said second clock rate to adjust itself to the said first clock rate. 51. The procedure under claim 50, whereby the acceptance procedure is further comprising a buffering step of at least the aforementioned predetermined number of network information bits and at least the aforementioned predetermined number of data bits. 52. The method under claim 51, whereby the aforementioned determination procedure is further comprised of a procedure for determining the difference between the rate at which at least a predetermined number of network information bits and at least a predetermined number of data bits enter the buffer and the rate at which at least a predetermined number of network information bits and at least a predetermined number of data bits exit the buffer. 53. The procedure under claim 52, whereby the determination procedure is further comprised of a step for establishing a lower threshold for rate differences. 54. The procedure under claim 52, whereby the determination procedure is further comprised of a step for establishing an upper threshold for rate differences. 55. The procedure under claim 50, whereby the procedure for setting at least one network information bit to a predefined value is further comprised of the following rate difference procedure: setting at least one network information bit to a predefined value representing the second clock offset state when the obtained rate difference is less than the upper threshold of the rate difference and greater than the lower threshold of the rate difference; and setting at least one network information bit to a predefined value representing the third clock offset state when the obtained rate difference is greater than the upper threshold of the rate difference. 56. The procedure under claim 55, whereby the procedure for transmitting to instruct the receiver operating at the second clock rate to adjust itself to the first clock rate, is further comprised of the procedure for transmitting the first clock offset state to instruct the receiver to subtract one data bit from a predetermined set of data bits, and the procedure for transmitting the third clock offset state to instruct the receiver to add at least one bit from a predetermined set of data bits. 57. The procedure under claim 50, whereby the setup process includes additional steps for pre-correcting at least one bit of the network information error. 58. Method for Clock Rate Matching Between Independent Networks in a Data Interconnect. The data interconnect uses a receiver with at least one serially transmitted data transfer frame as input. The data transfer frame contains at least a predetermined number of network information bits and at least a predetermined number of data bits, transmitted at the second clock rate. The predetermined number of network information bits contains at least one bit representing at least one clock offset state. The method consists of the following steps: receiving at least one data transfer frame containing at least the predetermined number of network information bits and at least a predetermined number of data bits transmitted at the second clock rate; determining the clock offset state in response to the receipt of the predetermined number of network information bits; switching at least one bit from the received predetermined number of data bits in response to the determination step; and matching the second clock rate to the first clock rate in response to the switching step. 59. Method pursuant to claim 58, whereby the procedure for determining the clock compensation state is further comprised of a procedure for determining at least one state of the first, second, and third clock compensation states. 60. The procedure under claim 59, whereby the procedure for swapping the said predetermined number of data bits by at least one bit, is further comprising a procedure for subtracting one bit from the said predetermined number of data bits, in response to the procedure for determining the result of the first clock offset state, and for adding the said predetermined number of data bits by at least one bit in response to the procedure for determining the result of the third clock offset state. 61. Method of Clock Rate Matching Between Independent Networks in a Communication System. A communication system uses at least two interconnects: a first interconnect and a second interconnect. The first interconnect uses a transmitter with at least a certain number of network information bits and at least a certain number of data bits transmitted at the first clock rate as input. The second interconnect is connected to a receiving network with a third clock rate. The method consists of the following steps: At the first interconnect, the second interconnect receives the second clock rate signal; At the first interconnect, at least a predetermined number of network information bits and at least a predetermined number of data bits transmitted at the first clock rate; At the first interconnect, the rate difference between the first and second clock rates is determined; At the first interconnect, the rate difference is determined between the first and second clock rates; At the first interconnect, and in response to the determination step, at least one network information bit is set to a predetermined value to represent the selected clock offset state; and At the first interconnect, the clock rate is matched. At least one network information bit representing the selected clock offset state is sent to the second interconnect for reception. At the second interconnect, at least one network information bit representing the selected clock offset state is assigned. At the second interconnect, and in response to the reception of at least one network information bit, the selected clock offset state and switching at the second interconnect, and in response to the assignment step, the received data bit is multiplied by an integer multiple of the received data bit to match the second clock rate with the third clock rate. 62. In a radiotelephone communication system interconnected with a data network operating at a different clock rate relative to the radiotelephone system's data rate, the network transmits information to the radiotelephone system via ISDN frames. The radiotelephone system has a transmitter and receiver that send data rate compensation information. The method of compensating for the data rate difference involves the following steps: placing the data rate compensation information into two ISDN frames; transmitting the data rate compensation information to the receiver via those two ISDN frames; receiving the data rate compensation information from the receiver via those two ISDN frames; and compensating the data rate difference at the receiver with a multiple of an integer bit. 63. A radiotelephone communication system under claim 62 where the receiver is located within either a fixed-station cellular radiotelephone infrastructure or a mobile cellular radiotelephone. 64. Radio telephone communication system under claim 63, whereby the fixed cellular radio telephone infrastructure equipment is characterized as either a Base Station System (BSS), a Mobile Switching Center (MSC), or an Interworking Function (IWF). 65. In a radiotelephone communication system interconnected with a data network operating at a different clock rate relative to the radiotelephone system's data rate, the network transmits information to the radiotelephone system via ISDN frames. The radiotelephone system has a transmitter and receiver that send data rate compensation information. The method of compensating for the data rate difference consists of the following steps: determining the required compensation based on the data rate difference; generating data rate compensation information based on the required compensation; and instructing the receiver to compensate for the data rate difference with a multiple of an integer bit based on the data rate compensation information sent to the receiver via two ISDN frames. 66. A radiotelephone communication system pursuant to claim 65, where the transmitter is located within either a stationary cellular radiotelephone infrastructure or a mobile cellular radiotelephone. 67. Radiotelephone communication system under claim 66, whereby the fixed cellular radiotelephone infrastructure equipment shall be of a specific type, namely, a base station system (BSS), or a mobile switching center (MSC), or an interworking function (IWF). 68. In a radiotelephone communication system interconnected with a data network operating at a different clock rate relative to the radiotelephone system's data rate, the network transmitting information to the radiotelephone system via ISDN frames, the radiotelephone system has a transmitter and receiver that send data rate compensation information. The method of compensating for the data rate difference involves the following steps: determining the desired compensation based on the data rate difference; generating data rate compensation information based on that compensation; transmitting this compensation information via two ISDN frames to the receiver; receiving the transmitted data rate compensation information; and compensating for the data rate difference with bits that are multiples of an integer in response to the reception steps. 69. A radiotelephone communication system pursuant to claim 68 where the transmitter is housed within either a fixed-station cellular radiotelephone infrastructure or a mobile cellular radiotelephone. 70. Radiotelephone communication systems under claim 69, whereby the fixed cellular radiotelephone infrastructure equipment shall be characterized as either a base station system (BSS), a mobile switching center (MSC), or an interworking function (IWF). 71. In a communication system interconnected by networks carrying data operating at different clock rates, the communication system has a transmitter and a receiver that transmit data rate compensation information. The method of compensating for the data rate difference consists of the following steps: determining the required compensation based on the data rate difference; generating data rate compensation information based on that required compensation; instructing the receiver to compensate for the data rate difference with a multiple of an integer bit and providing data rate compensation information for at least two transmitted frames; receiving the data rate compensation information provided on at least two frames; determining the required compensation based on that data rate compensation information and compensating for the data rate difference with a multiple of an integer bit in response to the instructions; and finally, receiving the data rate compensation information provided on at least two frames. 72. Communication systems based on claim 71, whereby the generation of data rate compensation information is characterized by the creation of data rate compensation information based on the expected bit error rate of the communication system. 73. A communication system pursuant to claim 71 where the transmitter or receiver is located within either a fixed-station cellular radiotelephone infrastructure or a mobile cellular radiotelephone. 74. Communication system under claim 71, whereby the fixed cellular radio telephone infrastructure equipment is characterized as either a base station system (BSS), a mobile switching center (MSC), or an interworking function (IWF). 75. In a communication system interconnected by a network carrying data operating at different clock rates, the communication system has transmitters and receivers that transmit data rate compensation information. The method of compensating for the data rate difference involves the following steps: determining the required compensation based on the data rate difference; generating data rate compensation information based on that required compensation; providing data rate compensation information for transmission over at least two frames; receiving such data rate compensation information provided over at least two frames; determining the required compensation based on that data rate compensation information; and compensating for the data rate difference in response to the generation step. 76. A communication system pursuant to claim 75 where the transmitter or receiver is located within either a fixed-station cellular radiotelephone infrastructure or a mobile cellular radiotelephone. 77. Communication system under claim 76, whereby the fixed cellular radio telephone infrastructure equipment shall be characterized as either a base station system (BSS), a mobile switching center (MSC), or an interworking function (IWF), or an interworking function (IWF). 78. In communication systems, particularly digital radiotelephone systems interconnected with data networks operating at different clock rates, the communication system transmits data rate compensation information in the form of 5-bit code words. In an ISDN frame, the compensation method for the data rate difference consists of the following steps: determining the required compensation based on the data rate difference; generating a 5-bit code word based on that required compensation; providing at least two 5-bit code words on the ISDN frame for transmission, where the 5-bit code word instructs the receiver to compensate for the data rate difference with a bit that is an integer multiple; compressing at least two ISDN frames into a standard air link format; transmitting the standard air link format through a radio frequency channel to a receiver that accepts the standard air link format; decompressing the standard air link format into at least two ISDN frames; determining the 5-bit code word provided on the at least two ISDN frames; determining the required compensation based on that 5-bit code word and compensating for the data rate difference with a bit that is an integer multiple in response to that step. 79. The communication system under claim 78, where compensation for data rate differences is provided by bits that are multiples of an integer, is also characterized by the prevention of the elimination of data rate compensation information during the compression and decompression processes of the communication system. 80. The communications system under claim 78, whereby the digital radiotelephone system is further characterized by at least one base station (BSS), mobile switching center (MSC), interworking function (IWF), or mobile system.