SU972592A1 - Storage cell - Google Patents

Description

The invention relates to computing technology and can be used to build semiconductor operational storage devices with low power consumption in the storage and recording mode and with improved speed when recording information.

There are known storage elements made on MOS transistors, containing a trigger and two elements, each consisting of a gate-controlled transistor. Paraphase with respect to each other, the recording signals are fed to the drains of pass-through transistors acting as keys in the recording elements. Such storage elements can be used in semiconductor storage devices for two-coordinate information recording | one.

Such schemes have relatively high performance, but drain control requires a significant power consumption over the write buses when recording information, which makes it difficult to organize large arrays of memory due to the need for powerful control stages.

The closest technical solution to the invention is a memory cell implemented on MOS transistors, containing a trigger with cross-coupling, two recording elements connected to the arms of the trigger and each performed on two keys. Each key is made on a single transistor controlled by the gate. Both elements of cell recording are made symmetrically with respect to the trigger inputs. When recording the input signals, it simultaneously opens one of the keys in each entry and

15 additionally, depending on the input signals, the second key is opened either in the first recording element or in second. Through two keys in series, a logical zero is written either to the left or right shoulder of the C2 trigger.

The specified memory cell with two consecutive keys in the record elements is not high enough

25 speed and also requires an increased key management voltage. This is due to the following reasons. When signals are triggered, the recording resolution, one of the transistors playing the role of a key in the recording element, opens and the voltage at its source begins to increase, which decreases the resulting gate voltage source and, consequently, increases the resistance of the key. In order for the resistance to change a little, it is necessary to increase the voltage on the gates of the transistors. In addition, in the given circuit, only one of the recording elements is included in each write cycle and, therefore, the parasitic capacitances of only one trigger arm are recharged through it, and the parasitic capacitances of the other trigger trigger are recharged through the high resistance of the load transistor of the trigger. This, in turn, reduces the speed of the memory cell during recording. The aim of the invention is to improve the speed when recording information at low power consumption. The goal is achieved by the fact that the memory cell, made on MOS transistors, containing a cross-connect trigger and recording elements, each consisting of two keys and connected to the trigger arms, additionally contains an inverter, and a third switch in each element recording, with etsm, the first key of the recording element is made on the first and second transistors with opposite types of conductivity, bounded by drains and sources and connected to the trigger arm, the second key is made on the n-channel third transistor, and the third - on the p-channel fourth transistor, connected by a drain to a common point of the first and second key, and drain by a positive polarity power source, the inverter is connected to the gates of the p-channel transistors of the first keys of each recording element, and the input is It is one of the entrances of the memory stick. The drawing shows a diagram of a proposed memory cell. The memory cell contains the trigger 1 two pairs of serially connected keys 2 and 4, inverter 4, keys 5 and b. The first key of each pair is made on two transistors 7, Q and 7, 8, and the second on transistors, 92, the third and fourth keys: 4 are filled with transistors 10 and 11. The trigger 1 of the memory cell is made with transistors 12-15, the inverter 4 is made on transistors 16 and 17, transistors 7, 10, 7, 11 ,, 12, 13, 16 - with the p-channel, transistors 8, 9a. 8, E, 14, 15, 17 - with the p-channel. Memorizing cell works as follows. If the inputs 18 and 19 of the transistors 16 and 17 are the voltage of a logical unit of positive polarity, and the input of the voltage is a logical zero, then the transistors 8. and 10 are opened and the transistor 7, the transistors 9 are opened by the voltage of the logical zero. and 11 are closed. Due to the implementation as a key of the transistor 10 with a p-channel and its source power, a low key resistance is provided, and the voltage on its drain increases during the transient process to almost i E, which reduces the key resistance on two transistors 7 and eight . During the transient process, the voltage at point 21 is below the threshold voltage of transistor 7, its resistance is high, but the channel resistance of transistor 8 is low, and the voltage at point 21 is higher than the threshold voltage of transistor 7, its channel resistance decreases transistor 8 increases. Such switching on ensures low key resistance at low and high levels, for example, at the hinge at point 21. The indicated switching on of two consecutive keys on transistors 10, 7 and 8j | provides low resistance of these keys during the entire transient process at low supply voltage low (control voltages at the gates. The VTO provides high speed with low power consumption both in the control circuits and in the power supply circuit. At the indicated voltages The x on the inputs 18-20 also opens the key on transistors 0, which works similarly to the key on transistors 7 and 8 and opens the key on transistor 9j, the resistance of which also remains quite low This is due to running it on the p-channel transistor and powering it down the drain. Thus, the resistance of the keys on the transistors 7, E also remains low during the entire transient process, ensuring high speed in writing. In the described case, in the left shoulder of the trigger 1 a logical unit is written, and a logical zero is written to the right shoulder of the trigger. If the inputs of cell 19 and 20 have the voltage of a logical unit of positive polarity, and the input 18 has a logical zero, then the open transistors 7, 8 are The keys 9 8-2 ;, 11 and the keys H are closed on the transistor 10 and the recording elements are made symmetrically with respect to the trigger inputs, therefore

the operation of the circuit is similar to that described with the only difference that the logical zero is written to the left shoulder of the trigger, and the logical one to the right shoulder of the trigger. ; The use of the proposed recording elements distinguishes the memory cell from the known one, since the recording speed increases;

low power consumption of control and power circuits. As a result, the speed increases.

(Information processing in computers.

The recording time of known memory cells on MOS transistors with two keys in the recording element is 80-100 NS, while the recording time of the proposed memory cell is 40-50 NS. If it is assumed that the full cycle of the memory block consists of the recording time and the polling time, then the gain in computer time will be approximately 25% of the total memory time.

Claims (2)

Invention Formula A memory cell containing a cross-linked trigger and two pairs of series-connected keys, characterized in that, in order to increase the speed of the memory cell, an inverter and third keys are inserted into it, the first key of each pair is made on the first and second transistors with opposite types of conductivity, the second key of each pair is made on the p-channel the third transistor, and the third on the p-channel quarter-turn transistor, the drains of the first and second transistors of each pair are combined and connected to the corresponding trigger arm, the drain of every third transistor is connected to 5, the drain of the respective fourth transistor and the combined drains of the first and second transistors, the gates of the third and fourth transistors are combined and are one of the inputs of the memory cell, the output 0, the inverter is connected to the gate of the first transistor, and the input is connected to the gate of the second transistor and is another input of the cell. five Sources of information taken into account in the examination 1. USSR author's certificate, 342222, cl. G 11 C 11/40, 1970. 2. USSR author's certificate 0 330490, class G 11 C 11/40, 1970 (prototype). OS / 7 ...