SU949833A1 - Receiving device - Google Patents

Description

(54) RECEPTION DEVICE

one

The invention relates to a technique for transmitting digital information and can be used to promptly receive information from many geographically dispersed correspondents at a center for collecting, storing and displaying information specified in digital form using PBX lines.

It is known that digital information on PBX lines is usually transmitted using devices that contain tone frequency generators by the number of channels and the control panel (for example, a dial pad). To address the transmitted information, each of the transmitters has an individual node of the marker signal identifying its place in the receiving device. When automatically receiving digital information, the receiving device has to allocate marker signals, as well as blocks for automatic reception of information, channel allocation and operational storage. 1.20

The disadvantage of such systems is the need for additional equipment for the generation of marker signals and decoding.

A receiving device with addressing information channels is known, which contains a series-connected control switch and a channel allocation unit, the outputs of which are connected to the first inputs of the n I elements, the outputs of which are connected to the corresponding inputs of the memory block 2.

The disadvantage of this device lies in the low reliability of the received information.

The purpose of the invention is to increase the reliability of the received information.

This goal is achieved by the fact that a receiver with addressing information channels containing serially connected control switch and a channel allocation unit, the outputs of which are connected to the first inputs of the n And elements, the outputs of which are connected to the corresponding inputs of the memory block, are entered n RS-trigger , an additional element AND and an element NOT, while the output of the element is NOT connected to the combined second inputs n of the elements AND, the output "Resetting the control switch is connected to

the combined R-inputs of RS-flip-flops, the C-inputs of which are combined with the input of the element NOT and are connected to the input of an additional element AND, to the inputs of which are under (The inverter outputs of the RS-flip-flop, the outputs of which are connected to moreover, the outputs of the channel allocation unit are connected to the S-inputs of the respective RS flip-flops.

The drawing shows a block diagram of the device.

The host device contains a control switch 1, a channel allocation unit 2, RS-triggers 3.1-З.п, a HE element 4, a AND 5.1-5.p element, an additional AND 6 element and a memory block 7 containing n address cells 8.1. -8 p.

The receiving device operates as follows.

When a connection is established, under the influence of the "Call from the PBX" signals, the control switch 1 is automatically turned on at the receiving side, which generates a "Reset" signal to the R inputs of the 3.1-3G Trigger RS and simultaneously connects the telephone line to the channel selection unit 2.

The "Reset" signal sets the RS-triggers 3.1-Зп to such a state that the logical "O" is set to the direct outputs, and the logical "1" to the inverse outputs.

Logical " O from the flip-flops are sent to the address cells 8.1-8 p, respectively, and are signals to prohibit the counters from these cells, hence they do not record whether the counting pulses from the channel allocation unit 2 are fed to the n-inputs in any of the n address cells or not.

The decree for writing to any of the address cells is only the presence of a logical "1 on its slit" Record.

At the same time, logical "1" from all inverse outputs of RS-flip-flops 3.1 is fed to the inputs of the element 6, from the output of which logical 1 is fed to the C-inputs, RS-flip-flops 3.1-Z.p and allows them to receive signals via S-inputs. In addition, the logical "1 from the output of the AND 6 element is inverted by the HE 4 element, and from its output, the logical" O is fed to the first inputs of the AND 5.1 - 5.P elements, thereby additionally prohibiting the passage of pulses to the address cells 8.1-8 .P. This is the initial state of the receiving device after the establishment of the connection via the PBX.

When using a preliminary pulse of one of the frequencies available in the transmitting device as a marker signal, the whole task is to separate this pulse from the entire subsequent series

carrying digital information pulses and using it for:

-inclusion of the desired address cell (submit for the time of receiving information logical "1 to bus" Record i channel;

- supplying the permitting signal (logical "1) to the elements AND 5.1-5. p transmitting information account pulses from each channel of the channel allocation unit 2 to the inputs of the address cells 8.1 to 8. p;

- supplying a locking signal (logical "O) to the C-inputs of all RS-flip-flops 3.1-З.п, thereby fixing their state after the passage of the marker pulse.

There are as many frequencies for manipulation on the transmitting device as there are types of information transmitted. Each of these frequencies (it is also an individual marker signal) when transmitting digital information is selected in the channel allocation unit 2 by appropriate filters, detected, and at the output of each channel, the received information is represented by a sequence of logical "O and logical" L equal to the number transmitted pulses (i.e., a digit dialed on the transmitting side).

.So, when sending a marker to the sending device. (first) pulse (for example, for the 2nd transmitting subscriber to form a marker pulse

0 uses the frequency of the 2nd channel, and its lane. Sonal Addresscheck - 8.2) last, after the selection, in the form of a logical "1 from the output of the block 2, the channels will go to the S-input of the RS flip-flop 3.2, which will cause it to roll over, i.e., on the" Record

5 channel II allows for recording of a 8.2 cell, and only it has a logical "1. At the same time, from the inverse output of this RS flip-flop 3.2, the input of element I 6 will receive a logical “O, which, in turn,. will cause the appearance at its output of the logical “O. This signal, arriving at the C-inputs of the flip-flops, will record their state, i.e., all but the 2nd one will remain in the original state, and the pulses arriving through any channel of selection

5 will not be able to change their states.

In addition, from the element NOT 4 logical "1 will go to the first inputs of the elements And 5.1-5. P, which will allow the passage of counting pulses through them from the allocation channels of block 2 to the address cells

° 8.1-8p.

This is where the choice of the address cell 8.1-8.p and its bringing into readiness (in the exploded example, only cell 8.2) to receive digital information is completed. Selection

Claims (2)

5 Other cells by their subscribers is carried out similarly to the above example. The use of the proposed device allows to improve the performance and reliability during its operation, to expand its functionality, to improve the quality and reliability of the transmitted and {1) information. By eliminating additional equipment, the cost of data transmission equipment is reduced. Claims Receiving device with addressing information channels containing serially connected control switch and channel allocation unit whose outputs are connected to the first inputs of the AND elements, whose outputs are connected to the corresponding inputs of the memory block, in order to increase the reliability of the received information entered into it n RS-flip-flops, an additional element AND and element NOT, while the output element is NOT connected to the combined second inputs n elements AND, the output "Reset control A switch is connected to the combined R-inputs of NC triggers, the C-inputs of which are combined with the input of the element NOT and connected to the output of the additional element I, the inputs of which are connected to inverse RS-flip-flop outputs, the outputs of which are written to the information inputs of the memory block and the outputs of the channel allocation unit are connected to the S-inputs of the respective RS flip-flops. Sources of information taken into account during the examination 1. USSR author's certificate No. 564723, cl. H 04 I 3/02, 1975. 2. USSR author's certificate number 489237, cl. H 04 L 1/04, 1974 (prototype). ff-jif