SU947747A2 - Ultrasonic echo-pulse flaw detector - Google Patents

Description

This invention relates to non-destructive testing and may be used to configure and test ultrasonic instruments.

According to the main av1.sv. No. 627397 is known ultrasonic pulse-echo flaw detector containing, after connected, synchronously connected, a probe pulse generator, a selector amplifier whose input is connected to the synchronizer output, and a recorder, a transceiver connected to the probe pulse generator, a cascade of matches and delay stage, as well as serially connected start stage, first trigger, modulating voltage driver and modulator whose input is connected to the output of delay stage, and output d to an input amplifier, a counter, - whose input is connected to the output kaskadazaderzhki, and the first output - to an input of the flip-flop and the second flip-flop, a first input of which is connected to the second input of the counter, the second input - to the output of trigger stage as well. the output is to the first input of the kagskad coincidence, the second input is connected to the output of the synchronizer, and the output to the input of the cascade of delay 1.

The drawback of the device is the low reliability of the control at a high scanning speed, since the device lacks the ability to adjust in the dynamic mode. ,

The purpose of the invention is to increase the reliability of control.

The goal is achieved by the fact that the device is equipped with a delay control control button, connected between the output of the modulating voltage generator and the second input of the delay stage, an adder connected between the modulator output and the amplifier input, and a series connected by a noise generator and an element And, the second input of which is connected to the output of the first trigger, and the output - to the second input of the adder.

The drawing shows the block diagram of the instrument.

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The ultrasonic pulse echo flaw detector contains a synchronizer 1, a generator 2 probe pulses, an amplifier 3, a selector 4, whose input 30 is connected to the output of synchronizer 1, and a transmitter and transmitter b, connected to the generator output 2 probe pulses, a cascade 7 coincidence and a casc 8 delay, as well as serially connected start cascade 9, the first trigger 10, the modulating voltage driver 11 and the modulator 12 whose input is connected to the output of each delay 8, and output - to the input of the amplifier 3, the counter. 13, the input of which is connected to the output of the delay stage 8, and the first output to the input of the trigger 11, and the second trigger 14, the first input of which is connected to the second output of the counter 13, the second input to the output of the launch stage 9, and the output to the first input of the cascade 7 matches, the second input is connected to the output of the synchronizer 1, and the output to the input of the delay stage also contains a delay control block 15 connected between the output of the modulating voltage generator 11 and the second input of the delay stage 8, the adder 16 connected between the output of the modulator 12 and by the entrance forces tep 3, and serially connected noise generator 17 and AND gate 18, a second input coupled to an output of the first flip-flop 10, and output to the second input of the adder 16. The flaw detector operates as follows. Synchronizer 1 starts a generator of 2 probe pulses that excites converter 6. Reflected echo signals from defects across the amplifiers 3 and selector 4 are fed to recorder 5. When scanning the input of amplifier 3, a pulse pattern is formed, the envelope of which has the shape of a bell. When setting up a flaw detector, the scan mode is simulated. At the same time, the impulse coming from the launch stage 9 to one of the trigger 14 inputs translates it into and opens the coincidence stage 7, and the impulses arriving at its input from the output of synchronizer 1 start the delay stage 8. Cascade 8 provides a delay for each burst of a burst relative to the sync pulse in order for burst pulses to enter the flaw detector control zone, which is generated in selector 4. The burst pulses from the output of the delay bar 8 arrive at a counter 13, which, after the eighth pulse, for example, generates on its

output reset signal in

trigger 14,

The counter 13 also generates a signal to reset the trigger 10 after the arrival of, for example, four pulses. Shaper 11 of modulating voltage ps impulses impulse from trigger 10, which forms it under

Claims (1)

1. USSR author's certificate No. 627397, cl. G 01 N 29/04, 1974 (prototype).