SU926786A1 - Digital demodulator of relative phase-shift keying signals - Google Patents

Description

(B) DIGITAL DEMODULATOR SIGNALS RELATIVE PHASE MANIPULATION

I

The invention relates to a communication technique and can be used in discrete messaging systems for receiving relative phase shift signals.

A digital demodulator of relative phase shift keying signals is known, which contains a trigger and a serially connected input driver, a clock selection unit and a first counter, the outputs of which are connected to the inputs of the decoder, the first output of which is connected to the first trigger input, and the reference frequency generator, output which is connected to the clock inputs of the clock selection unit and the first counter, 1.

However, such a demodulator has low noise immunity at different levels of interference in the communication line.

The purpose of the invention is to improve noise immunity at various levels of interference in the communication line. .

The goal is achieved by the fact that, in a digital demodulator, relative phase shift keying signals comprising a trigger and a serially connected input driver, a clock selection unit and the first counter, whose outputs are connected to the decoder inputs, the first output of which is connected to the first trigger input, and generator

10 of the reference frequency, the output of which is nori is keyed to the clock inputs of the clock selection unit and the first counter, the second counter and the element And whose output is connected are entered

15 to the second input of the trigger and the first input of the second counter, the outputs of which are connected to the additional inputs of the decoder, the second output of which is connected to the first input of the element I, the second input and output of which are connected respectively to the second output of the clock selection unit and the second input of the first counter 392678 ka, while the output of the reference frequency generator is connected to the clock input of the second counter, the second input of which is connected to the third output of the clock selection block, and the output of the AND element is connected to the control The decoder input, the decoder contains two discriminators and a deciding unit whose inputs are connected to the discriminator outputs, the inputs of which are decoder inputs, the outputs of the decision block, and the corresponding discriminator inputs are from the decoder control input, and the "clock selection unit contains two 0-flip-flops, an inverter and an OR element, whose inputs are connected to the first outputs of the O-flip-flops, while the input of the clock-selection unit is the first input D-flip-flop, the first output of which is connected to the first input of the second O-flip-flop, the second input of which is connected to the output of the inverter, the input of which is connected to the second input of the first O-flip-flop and is the clock input of the clock selection unit, the outputs of which are The first and second outputs of the second O-flip-flop and the output of the OR element, each discriminator contains an AND element and two O-flip-flops, the outputs of which are connected to the inputs of the AND element whose output and the second output of the second O-flip-flop are The waters of which are the corresponding inputs of the O-flip-flops, in addition, the decision block contains the AND element and the first and second OR elements connected in series, and the inputs of the AND element and the first OR element are the inputs of the decision block, whose outputs are the output of the AND element and the second element OR the second input of which is connected to the output of the element AND, FIG. Figure 1 shows the structural electrical circuit of the demodulator; in fig. 2 is a structural electrical circuit of the clock selection unit; in fig. 3 shows the demodulator input and output signals of the demodulator i, the digital demodulator of the relative phase shift keying signals contains the input signal generator 1 of the clock frequency selection unit 2. 5 the first counter 3, the decoder H, the trigger 5, the second counter 6, the element And 7 the generator 8 reference frequency, the decoder contains two discriminators 9 and 10 pulses in the code, and the second counter 6 - pause signal. The counter size depends on the frequency fftn and the message transfer rate. The choice of the value of fort, in turn, is determined by the desired value of the constant integration. Since digital technology has adopted a binary system and uses, as a rule, binary counters, it is advisable to choose fon 2. f-, ft 1200-800 Hz message transfer rate. Than the more n, the more accurate phase locking, the more constant the integration, but the higher the counter size. 3 this entails an increase in hardware. Therefore, the value of n must be chosen from a reasonable compromise. Modern integrated circuits of counters contain a counter for 8 bits in one case, that is, .P 8. At the same time, it is desirable that the frequency fp be less than 1 MHz, since modern cost-effective integrated circuits in CMOS technology work in the frequency range up to 1 MHz . By choosing p 7, we get fon 2 ft 128 {1200-А800) 153 6-6lt, kHz. At such values of the ffln frequency, almost all domestic microcircuits 1 or O work steadily in relative phase shift are transmitted by different pulses (FIG. A) depending from the sequence of transmitted pulses. In the case of ideal signals when receiving symbol 1, each counter 3 or 6 counts the pulses of frequency 128fT from O to 63, and the sequence of operation of counters can be any for one clock cycle: 1.5 and 6 clock cycles (FIG. 4d , e) at first the count 3 works | converts the duration of the pulse signal into a code, and then counter 6, which converts the duration of the pause signal into a code. In cycles 3 and 8 (fig. D) and the decisive block 11, the block 2 of the allocation of the clock frequency consists of two O-triggers 12 and 13, the inverter 1 and the element OR 15, each discriminator 9 and 10 contains two O-trigger 16- 19 and element 20 and 21, and decider 11 includes element 59 and 22 and the first and second elements OR 23 and 2. The digital demodulator of relative phase shift keying signals works as follows. The input signal generator 1 matches the link with the demodulator itself, to the input of which a signal arrives (Fig. 4a). Pulse tu-ff pulses are generated from the phase-out of the pulsed signal in block 2 of the clock frequency distribution (Fig. 4c) coinciding in time with the pulses from the reference frequency generator 8 (Fig. B) and corresponding to the zero crossing signals (Fig. Ka). Fasomanipulated the signal arrives at the information input of the 0-flip-flop 12, the information is written to the O-flip-flop 13 with a delay tsae 2fon) as a result of the output of the OR 15 element, a signal is generated, the pulse duration of which is 2fon ° (fig. tie). Since the used triggers are clocked by the frequency of the reference frequency generator 8, the information from the outputs of the clock extracting unit 2 is linked to the fon frequency of the reference frequency generator 8 used in further signal processing. Errors due to non-phase sequence of the clock pulses of the generator 8 reference

However, due to the edge distortions, crushing and displacement of the characteristic moments of the recovery of the parcels in real communication channels, the duration of the pulse and pause signals may vary. In this case, situations arise when the duration of the pulse signal is not exactly equal to the duration of the pause signal or the duration of the pulse signal (pause) is not equal to the exact value selected in advance. The codes at the output of the counters change accordingly. For a particular communication channel, well-defined interference is characteristic.

Claims (3)

To increase the reliability of the received information 8, the composition of the decoder i introduced discriminators 9 and 10, 6 frequencies and sequences of received (- "pulses of the signal of relative phase shift keying will be eliminated. The pulse and pause signals are integrated by the first and second counters 3 and 6, and the first counter 3 converts the duration of the signal, the sequence of operation of the counters will be different. If the codes taken from counters 3 and 6 coincide, the decoder 4 generates a signal 1. When receiving the symbol O, as can be seen from FIG. o counter 3 (2 and 7 cycles), or counter 6 С tact). In this case, any counter counts 128fT frequency pulses from 0 to 128. The counting signal for any counter is a logical signal 1. In other words, information that symbol 1 is present at the input of the demodulator when the pulse signal duration and the pause signal are equal, which must (, prices be equal to Tpgf ff 1200 Hz, tuMrt t pause 27T20bHz if 17. ISS. Information that the symbol O is present at the input of the demodulator, if the duration of the pause signal is -; - 83 ISS. 1200 Hz. The operation of the decoder k can be described as follows. truth table: which ensure the preservation of the required information when the duration of the input signals varies within certain limits Discriminators 9 and 10 are identical, performed on two D-triggers 16 and 17 (or 18 and 19) and one element AND 20 (Fig. 3) Infor The ma- chine input of each discriminator D-flip-flop is connected to the higher bit of counter 3 or 6 (Fig. 3). In such a construction of the discriminators, the D-flip-flop 16 (18) goes into one state with the arrival of the 487 th pulse of the fim frequency - 128fT and is reset to zero state by the 80th pulse. D-flip-flop 17 (19) enters the unit state with the arrival of the 96th pulse and is reset to the zero state by the 136th pulse of the frequency fon. Two windows are formed in the discriminator 9 (10): pulses and 96-136 pulses. Thus, symbol 1 will be received correctly, even if, for example, tuvun 50 frequency pulses 128f, a) bi 78 frequency pulses Symbol O is received correctly if tuvjun Ct nayjbt) changes within window 96-136 pulses frequency 128fr , the O-flip-flop 16 and 18 are involved in the formation of the pulse signal during the deciphering of the symbol 1 (Fig. 3) When the O symbol is decrypted, it works or the D-flip-flop 19- Gives an exact transition to one state of any of the D-flip-flops 17 or 19 to form an output pause signal (see truth table). the output of the decoder signals is generated by the decision block 11. The information signal is removed from the output of the AND 22 element (Fig. 3) and from the output of the OR 2k element is the clock si Nal (Fig. | (g). From the output of the decision block 11, the clock signal arrives To the input of the element 7, to the second input of which a gating signal is output from the output of the clock separation unit 2. The output clock signal of the demodulator is taken from the output of the element 7 and it also enters the zero input of counters 3 and 6 and discriminators 9 and 10, resets them to zero state, thus preparing for the analysis of the next input symbol (Fig.). The output information signal of the demodulator connected in phase K to the output clock signal is removed from the output of the O-flip-flop 5 (Fig.). The technical and economic effect of the described demodulator of the relative phase signals manipulation consists in increasing the noise immunity, which is achieved by determining the duration of both the pulse and the pause of the input signal, comparing them, and also using a decoder containing discriminators. Performing the clock allocation unit in the manner described makes it possible to reduce the instability requirements and the correspondence of the reference frequencies of the transmitting and receiving equipment, as well as to ensure operation during short-term fades in the communication channel. 1. A digital demodulator of relative phase shift keying signals comprising a trigger and a serially connected input driver, a clock selection unit and a first counter, the outputs of which are connected to the inputs of the decoder, the first output of which is connected to the first trigger input, and the reference generator a frequency whose output is connected to the clock inputs of the clock selection unit and the first counter, characterized in that, in order to increase the noise immunity at various levels x interference in the communication line, entered the second counter and the element And the output of which is connected to the second input of the trigger, and the first input of the second counter, the outputs of which are connected to the additional inputs of the decoder, the second output of which is connected to the first input of the element And, the second input and the output of which is connected respectively to the second output of the clock selection unit and the second input of the first counter, while the output of the reference frequency generator is connected to the clock input of the second counter, the second input of which is connected to the third output The clock selection unit has one clock and the AND element output is connected to the control input of the decoder. 2. The demodulator of claim 1, which is that the decoder contains two discriminators and a decision block, the inputs of which are connected to the outputs of discriminators whose inputs are the decoder inputs of which are the outputs of the decision block and the corresponding inputs discriminators are the control input of the decoder. 3. Pop demodulator, 1, characterized in that the clock selection unit contains two 0-flip-flops, an inverter and an OR element, whose inputs are connected to the first, D-flip-flop outputs, and the input of the clock-selection unit is the first first input 0-flip-flop, the first output of which is connected to the first input of the second D-flip-flop, the second input of which is connected to the outputs of the inverter, the input of which is connected to the second input of the first D-flip-flop and is a clock input of the clock selection unit, the outputs of which are the first and the second output of the second O-trigger and the output of the element OR. 6 k. A demodulator according to claim 2, characterized in that each discriminator contains an AND element and two D-flip-flops, the outputs of which are connected to the inputs of the And element, the output of which and the second output of the second 0-flip-flop are the outputs of the discriminator, whose inputs are the corresponding inputs O-Triggers. 5. A demodulator according to claim 2, characterized in that the decision block contains an AND element and the first and second OR elements connected in series, and the inputs of the AND element and the first OR element are the inputs of the decision block, the outputs of which are the output of the AND element the output of the second element OR, the second input of which is connected to the output of the element I. Sources of information taken into account during the examination 1. USSR author's certificate (G 605332, class H L 27/18, 1976. "Mmmmmmm w-rr $ rr V stf 13 rr Yy Mr Sh. u F J) t1 13 Tf IG 18-19 It AftMT t SMT. L Ijw and 14 Tffxm ./ / / Av: Mf 94.f Itm. SS.I J IftfM.