SU922879A1 - Fixed storage protection device - Google Patents

Description

The invention relates to storage devices.

A device for protection of permanent memory is known, which contains a buffer register encoding and decoding blocks, a shift number counter, ^{I * * * 5}

node stretching-compression of words in time and the control unit [1].

A disadvantage of this device is the inability to correct errors such as precipitations or insertions of characters. '

The closest to the offered technical solution for a device comprising an encoder for protecting non-volatile memory, a first switch, whose output is connected to the input of counters ¹⁵ snip words, the output of which is connected to the input of the first control unit, whose output is connected to the input of block formation marker, yield which is connected to the input of the first switch, the control input of which is connected to the second output of the first control unit, the output of the first switch connect2

with long-term memory input, the output of which is connected to the input of the marker selection block, the character counter between the markers and the second switch, the second input of which is connected to the memory output, the output of the marker allocation block is connected to the input of the character count counter between the markers, the output of which is connected with the input of the comparator, the output of which is connected to the input of the second control unit, the output of which is connected to the control input of the second commutator, the output of which is connected to the input of the decoder I2

A disadvantage of this device is the need, when falling out or inserting symbols, to supply each word with its own marker to restore word synchronization, i.e. record a significant amount of redundant information, resulting in reduced reliability of control.

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The purpose of the invention is to increase the reliability of the control permanent memory. '

This goal is achieved by the fact that the device for monitoring the permanent memory containing the coding unit, the main driver of the marker signal, the first local control unit, switches, the first word counter, the marker extraction unit, the signal counter, the main drive, the comparison circuit and the decoding unit, moreover, the input and output of the main driver of the marker signal are connected respectively to the first output of the first local control unit and to the first input of the first switch, the output of which is ervym output device and connected to the input of the first '

the word counter, the output of which is connected to the input of the first local control unit, the second output of which is connected to the control input of the first switch, the first input of the second switch is the first input of the device and is connected to the first input of the signal counter and the input of the marker selection signal, the output of which connected to the second signal input ³ of the counter whose output is connected to the input of the comparison circuit, the first output of the second switch is connected to the input of the decoding unit, a second input and an output of the second commutator 3 Torr are respectively connected to the first output and the input of the main storage, second and third inputs of which are respectively connected to first and second outputs of the second Bloch ka mestnogoupravleniya ^4, the third output is connected to the control input of the second switch and the first input - with the output of the comparison circuit, the input of block coding is the second device's ^4th input, buffer registers are entered, modulo-two adders, keys, shift register, additional marker generator, additional storage, synchro-5 , the second word counter, the information register, the address signal shaper and the AND elements, the input of the first buffer register connected to the output of the coding unit, and the 5 output to the second input of the first switch and the first input of the first modulo two, the second input of which is connected to the third the input of the first switch and the output of the shift register, and the output with the first input of the first key, the second input of which is connected to the third output of the first local control unit, the output of the first key is connected to the input of the shift register, the first and The second inputs of the additional marker signal shaper are connected respectively to the output of the marker selection block and to the output of the signal counter, the control input and the output of the additional marker shaper signal

5 are connected respectively to the fourth output of the second local control unit and to the second input of the second local control unit and the first input of the synchronizer, the second input, which is connected to the output of the comparison circuit, and the output to the fourth input of the main drive and the first input of the address generator, the second the input of which is connected to the first output of the decoding unit, the first input of the first element I and the input of the second counter layer, the output of which is connected to the third inputs of the address signal shaper and the second local control locale, the fifth output of which is connected to the fourth input of the address signal shaper, the output of which is connected to the first input of an additional storage device, the second input of which is connected to the first output of the second key, the first input of which is connected to the output of the first And element, and the second input to the second output block decoding and the first input of the second modulo two, the second input of which is connected to the first output of the third key, and the output - to the input of the information register, one of the outputs of which is connected to the first th input of the third key, and other outputs of the information register are connected respectively to the inputs of the second element And, the output of which is connected to the fourth input of the second local control unit, the sixth output of which is connected to the second input of the first element And, the second output of the second key is connected to the input of the second buffer register The output of which is connected to the first input of the third modulo-two adder, the second input of which is connected to the second output of the third key, the second

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the input of which is connected to the seventh output of the second local control unit, the first output of which is connected to the first control input of the synchronizer and the third input of the additional storage drive, the fourth input of which is connected to the second control input of the synchronizer and the second output of the second local control unit, the output of the third adder ^{, 0 is} connected to the fifth input of the additional drive, the output of which is the second output of the device.

The drawing shows a functional diagram of the proposed device. ¹⁵

The device contains a coding block 1, the main driver 2 of the marker signal, the first buffer register 3, the first adder 4 modulo two, the first block of local control 5, the first key 6, the first switch 7, the shift register 8, the first counter 9 words. The drawing also shows a monitored permanent memory 10. The device also contains a block 11 of the marker signal division, ^{25, a} signal counter 12, a second switch 13, an operative type main storage 14, an additional marker signal generator 15, comparison circuit 16, a block 17 decoding, additional storage 18 of operational type, second local control unit 19, synchronizer 20, second word counter 21, second buffer register 35, register 22, second modulator 23 modulo two, information register 24, first AND 25 element, formed Spruce 26 address signals, a third adder 27 of modulo two, the second AND gate 28, 40

second 29 and third 30 keys. Registers 8 and 24 each contain η digits, where n is the length of the code word.

The device works as follows.

The information stored in the permanent memory 10, to the input unit 1 through the register 3 and ~ second input switch 7 and the first input of the adder b, to the second input of which is ⁵⁰ steps po- information output from the register 8. The output of the adder 4 via the key information 6 enters the register 8. After the transfer to the code words in the register 8, the (k + 1) word is formed, ⁵⁵ representing the result of modulo two by the code words.

The first input of the switch 7 receives a marker from the output of the block 2 of the formation of the marker, and the third input information from the register 8.

Block 1 forms the BCH code (n, m), where η is the length of the code word; t the number of information symbols correcting ί errors.

For recording in the permanent memory 10 information from the output of the switch 7, the control unit 5 forms a frame, which consists of a marker of length M, k code words of length η and one word of length l parity. The total frame length is N = M + (k + 1) n, and the redundancy, or its reciprocal, code rate 8, is 8 = Ud + Τ ^ Τηη '

The choice of the parameters of the code, marker and the number of code words in the frame is due to, firstly, to provide the maximum possible 8 with a limited frame size Ν that satisfies the condition: N (P _6pr + 8 & οτ) <1, where 'P 6CT ” ^ve ° F ^yatn ° with ^five types of error symbol deletions and insertions, and secondly, it is desirable to select a value of 8 as a ratio of small integers, which is useful in the formation of coherent clock nets: input frame information and recording in the permanent memory 10.

When reading information from memory 10 is fed to the input of block 11, counter 12 and through the switch 13 t in drive 14. In block 11, a marker is allocated and a reference signal from the end of the marker is output, which is fed through the imaging unit 15 to counter 12, which determines the number of characters between markers, and the second input unit 19 controls. The counter 12 conducts a continuous count of the number of characters between the markers, which in the nominal is equal to the frame length N, and the result of the counting is transmitted to the comparison circuit 16 and to the second input of the imaging unit 15. the marker intended for recovery. If several frames in a row are dropped or inserted in the frame, and the packet character is typical of this, then the comparison circuit 16 detects and outputs to the second control block 19 a corresponding signal characterizing the difference between the nominal frame length and the calculated one.

In the event that the occurrence or insertion of characters falls on the marker itself, it cannot be selected and the counter 12

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count the number of characters close to,

2Ν, and the driver 15 outputs an intermediate reference signal to the synchronizer 20. This signal is formed so that the interval to 5

the next marker was exactly Ν.

On the basis of the reference signal from the end of the marker unit 19 controls the switch 13, cutting off the marker from the rest of the information when writing it to the accumulator ^{, 0} player 14.

Reading information from drive 14 through switch 13 to decode it by block 17 is performed according to words, for which the synchronization signal from the synchronizer ° 20 ^{, 5} is sent to the memory device 14. When the length of the received frame is equal to the nominal length, the signal of the synchronization is counted from the marker coming at the beginning of the frame.

In the case when the length of the received frame is not equal to the nominal length, the word synchronization signal can be counted from the marker arriving both at the beginning of the frame and at the end of the frame, depending on the control signals "read from the beginning" or "read from the end" supplied by the unit 19 ₃₀ controls to synchronizer 20 and accumulators 14 and 18. To generate a word synchronization signal, counted from the end of the frame, the synchronizer 20 receives a signal from the output of the comparison circuit 16, In the case where there are no upsets or insertions of symbols in the Frame, the block 17 performs word decoding starting from the beginning of the frame. Decoded information through the key 29 record! - 'goes to the additional drive 18. At the same time, the information from the output of block 17 goes to the first input of the adder 23, to the second input of which a signal comes from the output of the key 30, ⁴

the input of which receives a signal from the output of the register 24. Similarly, 'as when encoding information, after block 17 decodes (k + 1) a word, in register 24 a re- ^! parity check result. If among the decoded (к + Г) words in any of them the number of errors does not exceed I (the correcting ability of block 17), then in register 24 there are ^! one of the zeros and the element And 28 outputs the corresponding signal to the control block 19. If in one of the words the number of errors exceeds I, then block 17 performs incorrect decoding and, as a result, the contents of register 24 are not zero, which is a signal from AND 28 to block 19 of control. From the output of block 17, a signal is received that the number of errors in a word is equal to or greater than T. This signal enters counter 21, which counts the number of decoded words with the maximum number of errors, to the second input of the driver 26 and the first input of the AND 25 element if at its second input there is a prohibitory signal from the control unit 19, closes the first output of the key 29- This opens the second output of the key 29, from which the defective word is written to the registrar 22. The driver 26 determines the address of the erased word to the drive 18. If the number of such erased words' does not exceed one, then control block 19 outputs the corresponding signal to key 30 and to driver 26, as a result of which the contents of register 24 are summed in the adder 23 with the contents of register 22 and written to the drive по 8 at the corresponding address .

If there are errors such as dropping or inserting one or several characters in a row, the number of characters in the frame will be less or more Ν. The signals from the output of the comparison circuit 16 are received by the control block 19 and the synchronizer 20. Information is decoded from the beginning of the frame until, starting with the word in which the error occurred, block 17 does not give a signal that the number of errors is equal to or more. Moreover, due to the shift of the boundaries of this word, subsequent words are accompanied by the specified signal. Signals about this from the counter 21 are received in the control unit 19, which stops the decoding in the forward direction. The signal "read s.end", which is fed from the control unit 19 to the drive

18 and the synchronizer 20, block 17 start. starts word-by-word decoding from the end of the frame until counter 21 gives the corresponding signal to the block

19 and on the imager 26, which, based on the available information, calculates the address of the word at which the errors occurred, and which in

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the result is erased. When re-decoding a frame that is produced from the beginning and end of the frame, the erased word is not served in the '17 block. As a result, in register 24, in which 5 the result of the parity check of the entire frame is recorded, the desired corrected word is generated, which through the key 30, according to the control signal from block 19, is placed at its address Y in drive 18, from which the word enters the device.

Technical and economic advantages of the proposed device zaklyucha- ₁₅ etsya more highly! ^ Compared with the known reliability of the control non-volatile memory.

Claims (1)

Claims ²⁰ A device for protection of permanent memory containing a coding unit, a main marker signal generator, a first local control unit, switches, a first word counter, a marker signal extraction unit, a signal counter, a main accumulator, a comparison circuit and a decoding unit ₃ θ, and the input and output of the main marker driver are connected respectively to the first exit of the first block of seats * control and to the first input of the first switch, the output of which ³⁵ is the first output of the device and connected to the input of the first word counter, the output of which is connected to the input of the first local control unit, the second output of which is connected to the control input of the first switch, the first input of the second switch is the first and an input device connected to the first input of the counter and the input signal ⁴⁵ You are a block dividing marker signal, the output of which is connected to the second input signals of the counter, the output of which connected to the input of the comparison circuit, " 50 the first output of the second switch is connected to the input of the decoding unit, a second input and an output of the second switch are respectively connected to the first output and the input of the main storage, second and third inputs koto- cerned ⁵⁵ are respectively connected to first and second outputs of the second local control unit, the third output which is connected to the control input of the second switch, and the first input to the output of the comparison circuit, the input of the coding block is the second input of the device, characterized in that, in order to increase the reliability of the control, it contains buffer registers, modulators two, keys, shift register , additional marker shaper, additional drive, synchronizer, second word counter, information register, address shaper and I elements, with the input of the first buffer register connected to the output coding unit, and the output to the second input of the first switch and the first input of the first modulo-two adder, the second input of which is connected to the third input of the first switch and the output of the shift register, and output ⁴ with the first input of the first key, the second input of which is connected to the third the output of the first local control unit, the output of the first key is connected to the input of the shift register, the first and second inputs of the additional marker signal generator are connected respectively to the output of the marker selection block and to the output of the sc The signal generator, the control input and the output of the additional marker signal generator are connected respectively to the fourth output of the second local control unit and to the second input of the second local control unit and the first input of the synchronizer, the second input of which is connected to the output of the comparison circuit and the output to the fourth input of the main drive and the first input of the address signal shaper, the second input of which is connected to the first output of the decoding unit, the first input of the first element And and the input of the second counter words, the output of which is connected to the third inputs of the address signal generator and the second local control unit, the fifth output of which is connected to the fourth input of the address signal generator, the output of which is connected to the first input of the additional drive, the second input of which is connected to the first output of the second key, the first input of which connected to the output of the first element And, and the second input to the second output of the decoding block and the first input of the second 11 922879 12 modulo two, the second input of which is connected to the first output of the third key, and the output to the input of the information register, one of the outputs of which is connected to the first input of the third key, and the other outputs of the information register are connected respectively to the inputs of the second And element, the output of which connected to the fourth input of the second local control unit, the sixth output of which is connected to the second input of the first element And the second output of the second key is connected to the input of the second buffer register, the output of which is connected to the first at the input of the third modulo adder two, the second input of which is connected to the second output of the third key, the second input of which is connected to the seventh output of the second local control unit, the first output of which is connected to the first control input of the synchronizer and the third input of the additional drive, the fourth input of which is connected to the second control input 5 synchronizer and the second output of the second local control unit, the output of the third adder is connected to the fifth input of the additional drive, the output of which is the second output of the device.