SU918947A1 - Device for automatic checking and correction of errors - Google Patents

Description

I

A device for automatic control and error correction is used when transmitting, registering and reading information encoded with a binary code.

A device for resetting decadiating cyclic codes is known, comprising a shift register, an adder, a buffer memory block, a control unit, a syndrome analyzer, a syndrome symbol adder, an error generator, and an alleged generator. error l. The disadvantage of this device is its low speed.

The closest in technical essence to the present invention is a memory device with error control comprising a memory unit, a group of registers, generators, switches, decoders, a comparator and a reconfiguration unit, while the outputs of the registers are connected to the corresponding inputs of the generator and switch, the outputs

which groups are connected to the comparator and generator, the outputs of which are connected to the decoders, the outputs of which are connected in series to the error detection units and the 2T reconfiguration unit,

A disadvantage of the known device is the low reliability of this device.

The purpose of the invention is to increase the reliability of the device.

To achieve this goal, a device for automatic control and error correction, containing an information parity generator and a disk parity generator, with the input of the information parity generator connected to the information input of the device, the input of the error control disk of which is connected to the input of the parity generator, a sign, correction unit, correction decoder, analysis unit, syndrome parity generator and generator generator, the first input (the second is the input of the device error control disk, and the second input is the formational input of the device, the output of the syndrome generator is combined with the input of the syndrome parity generator and the input of the analysis unit and is the output of the error control sign, the output of the information parity generator, the sign parity generator and the syndrome parity generator are connected to the corresponding inputs of the error control block, the output of the syndrome parity generator connected to the first input of the correction decoder, the second input of which is connected to the output of the generator syndrome, the third to the first output of the analysis unit, the second output of which is The device information output, the device error output is the output of the error control block, the first output of the correction decoder is connected to the first input of the correction block, the second and third inputs of which are connected respectively to the first and second inputs of the generator generator, the data correction output and the output of the error sign of the block The controls are the corresponding inputs of the device, the output of the correction decoder is the output of the uncorrected error of the device information.

The drawing shows the block diagram of the device.

The device for automatic control and error correction contains syndrome generator 1, information parity generator 2, disk emulator 3 generator, syndrome parity generator 4, error control block 5, correction block 6, correction decoder 7, and analysis block 8, data correction input 9 , input 10 for correction of the error control sign, input 11 for the uncorrected error, input 12 for the error, information input 13, input 14 for the error control, information information input 15 for the data, input 16 for the error control.

The information that comes in for encoding is fed to the data input information input, from where it enters the generator-1 input, the parity information generator 2 and the correction circuit 6 input. Error control sign of the received coded information enters the error control sign correction input. from where it is fed to the input of the syndrome generator 1, to the input of the generator 3 of the parity of the error control sign and to the input of the correction circuit 6, In case the device is used to encode information that is intended for or soap has to register in the memory, on the sign of the correction input of the control error is fed splat control of zero. The developed syndrome from the output of the generator-generator 1 is applied to the input of the k parity syndrome generator, to the input of the syndrome analysis unit 8, to the input of the error control sign and to the input

5 decoder 7 correction. The syndrome analysis unit compares the syndrome value with zero and, depending on the result of this comparison, either transmits an error-free code word P through the output of the syndrome analysis unit 8 to the information input of the information without error, or transmits the error to the output of the syndrome analysis unit 8, which is fed from there to

input decoder 7 correction. Based on the value of the syndrome, which is received at the input of the correction decoder 7, based on the parity of the syndrome, which is generated at the output of the syndrome 4 parity generator and fed to the input of the correction decoder 7, and on the basis of a single error signal, which is fed to the correction decoder 7, the correction decoder sorts the errors into uncorrectable ones, which is reported with the help of a signal at the output of the decoder 7 correction, which gives rise to the output of uncorrectable errors, and corrected ones for which it its first output generates a correction code, which is fed to the input of the correction circuit 6. The correction code in the correction circuit (8-1) calls the inverse in bits of the encoded information, which is fed to the input of the correction circuit 6, or an error control sign, which is fed to the input of the correction circuit, and the corrected information is obtained at the output of the correction circuit 6, which is connected to the input of the corrected data of the device, into the corrected check mark of the controller is at the output of the circuit 6, the correction, which is connected to the input of the corrected sign of the error check.

Claims (2)

The control of error-free operation of the device is based on the fact that the parity of the information to be encoded must be identical with the parity of the error control sign, if the encoding is correct, otherwise the parity of the syndrome should be absent. The parity block of the error control sign performs an unequal operation over the value of the parity of information that is generated at the output of the generator 2 and is fed to the input of the block 5i. The parity of the sign of the error control is generated at the output of the generator 3 of the parity of the error control sign and is fed to the input of the Sf block parity of the syndrome is generated output of the generator i of the parity of the syndrome and enters the input of the unit 5. The value of the unit at the input of the error is a malfunction of the device, indicating a malfunction in the equipment of the device and This is not a satisfactory one. nom result of control and correction of information. The detection of a triple error, which causes a malfunction of the entire constructive module, which contains blocks for transmitting, registering and reading three bits, is based on the grouping of bits, the columns of which in the control matrix on the unevenness table other than zero, are set so that the syndrome generated at the output of the syndrome generator 1, is interpreted by the analyzer 8 syndrome block of the syndrome analysis as an error sign, and the location of the bits, which are indicated in the table by the same letters from A to Z in the last e 'roll pin matrix leads to signaling on the common triple error, which is caused by disruption of the entire structural unit, via syndrome, which has a value of units in place of the first and third bits left. The proposed device can be used when registering data in the memory of a digital system and re-reading this data, for example, in contact with the intermediate memory or working memory of automatic computing devices, minicomputers, microprocessors, calculators, digital telephone exchanges or measuring systems, and then when transferring data between digital systems, between their central processors, between channels and peripheral devices. An apparatus for automatic control and correction of errors. Containing an information parity generator and a sign parity generator, wherein the input of the information parity generator is connected to the information input of the device, the sign of the error control of which is connected to the input of the sign parity generator, increase device reliability,. . a correction block, a decoder correction block, an analysis block, a syndrome parity generator and a generator generator, the first input of which is the input of the device error control sign, and the second input are entered as information input of the device, the output of the syndrome generator is combined with the input of the syndrome parity generator and the block input analysis and is the output of the sign of the error control, the output of the gene-; parity rater and information, parity generator and parity syndrome generator are connected to the corresponding inputs of the error control block, the syndrome parity generator output is connected to the first input of the correction decoder, the second input of which is connected to the output of the syndrome generator, the third one - to the first output | the second output of which is the information output of the device, the output of the error of the device is the outputs of the error control block, the first output of the correction decoder is connected to the first input of the block to rrektsii, second and soot- inputs are connected, respectively to first and second inputs of the syndrome generator, the output data block error correction and the sign output control, is .sootvetstvuyuschi- E input device, the correction of the decoder output is vyhdom uncorrected errors device information. Sources of information taken into account during the examination 1. USSR author's certificate Vf 552716, cl. G About F 11/10, 03/30/77. 2. US patent number 35737 8, cl. N About K 1/10, published 1971. 1b w fd eleven ten % w