SU877525A1 - One-bit full binary adder - Google Patents

Description

154) SINGLE-DISCHARGE FULL BINARY TUMPER

I

This invention relates to digital computing.

Of & esten is a one-bit full adder built on AND-NES elements, with the unification of the outputs of the NAND elements using pseudo-elements AND Mounting AND) 1).

The disadvantage of such an adder is the use of seven two-input and one three-input AND-NES elements, which accounts for the relatively high complexity of this adder.

The closest to the proposed is a one-bit full binary adder containing AND-NOT and NOT elements, the first and second inputs of the adder being connected to the inputs of the first AND-AND element and, respectively, to the first inputs of the second and third AND-NOT elements, the second inputs of which connected to the output of the cervical element IS-NOT; the outputs of the second and third elements AND-NOT are connected to the inputs of the first pseudo-element AND,

The output of which is through the first, element. NOT connected to the first inputs of the fourth and fifth elements AND-NOT, the second input of the fourth and first inputs of the sixth elements AND-NOT connected to the third input of the adder, the second inputs of the fifth and sixth elements AND-NOT connected to the output of the fourth element AND-NOT, the outputs of the fifth and sixth elements are NOT connected to the inputs of the second

10 pseudo-elements AND, the output of which through the-i through the second element is NOT connected to the output of the sum of the adder, the outputs of the first and fourth elements AND-NOT connected to the inputs of the seventh element

ts is AND-NOT, the output of which is connected to the transfer output of the adder L The disadvantage of this adder is the relatively large amount of equipment.

Claims (4)

As is well known for f 3, some systems of elements allow one to obtain additional logic functions by combining the outputs of the elements with the help of pseudo-elements, and the pseudo-elements of the pseudo-elements AND (mounting and). In particular, some economy equipped NIL is achieved by using pseudo-elements AND in known adders. Such a combination of outputs of elements is allowed, in particular,. elements of integrated injection logic. The functional elements of this system can have several logically equivalent outputs. The purpose of the invention is to reduce equipment. This goal is achieved by the fact that in a single-bit full binary adder, performed on the elements of integrated injection logic, containing the elements AND-NOT and NOT, the first and second inputs of the adder are connected respectively to the first and second inputs of the first element AND-AND and with inputs respectively of the first and second elements NOT, the outputs of which are connected with the inputs of the first pseudo-element AND whose output is connected to the input of the third element NOT the outputs of the fourth and fifth elements are NOT connected with the inputs of the second pseudo And, the output of which is connected to the input of the sixth element is NOT, the output of the seventh element is NOT connected to the transfer output of the adder, the third input of the sigmmalgor is connected to the first input of the second element AND-NOT and the input of the fifth element, AND-NOT multi-output, and the first the outputs of the first and second elements of the NAND are connected to the inputs of the third pseudo-element AND, the output of which is connected to the input of the seventh element NOT, the second output of the first element AND-NOT and the output of the Third element are NOT connected to the inputs of the fourth pseudo-element AND, out d is connected to a second input of the second AND-element and the input element of the fourth NOR second output of the second AND-NOT and sixth output of NOT circuit connected to said fifth rows WMOs pseudo AND, whose output is connected to the output of the adder sums ... The drawing shows a functional diagram of a one-bit full binary smzmator. The adder. Contains elements AND-NOT 1 and 2 with two outputs, the elements NOT. 3-9 and pseudo-elements AND (mounting - and Po-14; Inputs 15 and 16 of the adder are connected to the inputs of the element AND-NOT 1 and to the inputs of the elements NOT 3 and 4, the outputs of which are connected to the inputs of the pseudo-element AND 10. The first output of the elements AND-NO 1 and 2 are connected to the inputs of the pseudo-element AND 14, the output of which through the element NOT 9 is connected to the output 17 of the sum of the adder. the output of the element NOT 5 is connected to the inputs of the pseudo-element AND P, the output of which is connected to the first input of the element AND-NOT 2 and one element of the HE 6, the second. input of the element AND-HE 2 and the input of the element NO 7 are connected to the input 18 of the adder. The outputs of the elements HE 6 and 7 are connected to the inputs of the pseudo-element AND 12, the output of which is connected to the input of the element HE 8. The second output of the element D -NON 2 and the output of the element NOT are connected to the inputs of the pseudo-element AND 13, the output of which is connected to the output of the transfer of the adder. At the inputs 15,16 and 18 days of the mat, the values of ar are in, and are from: respectively, one-bit operands. According to the establishment of the transition process, the outputs I7 and 19 of the adder form the sum and transfer values of cor responsibly - b - c. () C (a, -b-ve.b, -hc-Co b ya -b, -) ve. ( ) a, iD, -c.va-bc.va.b.,. bc- --a - iC va 4S-vaib; iC.va, b, -c.;. (to -va-b -) - а ъ: | Уц (а-ь -у-Ь-1 the proposed adder is simpler than the known one, since it contains only two two-input AND –NI elements with two outputs and - seven elements are NOT, which allows it to be used in large integrated circuits, where the main requirement is the minimum number of outputs and the smallest size of the adder — the elementary cell of the device with a regular structure. Formula One-bit full binary adder built on elements of integrated injection logic, containing elements and -NON and NOT, the first and second inputs of the adder are connected respectively to the first and second inputs of the first NAND element and to the inputs of the first and second NO elements, respectively, whose outputs are connected to the inputs of the first pseudo-element AND whose output is connected to the input of the third element NOT, the outputs of the fourth and fifth elements are NOT connected to the inputs of the second pseudo-element AND whose output is connected to the input of the sixth element. NOT, the output of the seventh element is NOT connected to the transfer output of the adder, the third input of the adder is connected to the first input of the second element AND-NOT and the input of the fifth element NOT, characterized in that, in order to reduce the equipment, the elements AND-NOT. - made multiple-output, and the first outputs of the first and second elements AND-NOT connected to the inputs of the third pseudo-element AND, the output of which is connected to the input of the seventh element 15 sixteen about- Nn 1L ten 17 / 11 5. 6 iHE, the second output of the first NAND element and the output of the third element are NOT connected to the inputs of the fourth AND pseudo-element, the output of which is connected to the second input of the second AND-NOT element and the input of the fourth NO element, the second output of the second NAND element and the output of the sixth element is NOT connected to the inputs of the fifth pseudo-element I, the output of which is connected to the output of the sum of the adder. Sources of information taken into account in the examination 1, Handbook of digital computing processors and memory. Ed. B.N. Malinowski. Kiev, Technique., 1979, p. 184, fig.4.49 b. . 2. Budinsky Ya. Logic circuits in digital technology. M., Holy Hour, 1977, p. 129, ris.5.35 b (.prototype), 3.Budinsky J. Logic circuits in digital technology. M., Holy h. 1977, pp.91-92. 4. Microelectronics, 1977, v.6, issue 2-, p. 108-126, Fig.3.