SU873362A1 - Transistor inverter - Google Patents

Description

(54) TRANSISTOR INVERTER

The device is related to electrical engineering and can be used to convert a constant-17O high voltage level to an alternating or constant voltage of another level. Inverters and transistor switches with series-connected transistors are known in which chain alignment 1 is used to evenly distribute voltages between series-connected transistors. These inverters have reduced reliability because these equalizing circuits do not eliminate overvoltages and overcurrents in transistors in switching processes. Closest to the proposed one. by its technical essence, it is an in- and out-turn, containing two chains of N-series-connected transistors connected to the output in | Lvod, the equalizing chains are made in the form of rectifiers, the rectifier inputs are connected to the additional windings of the output transformer, and the outputs are bypassed by a capacitor and included between the symmetric with respect to the output output of the points of connection of the transistors in one and the other chain 2. Because of the variation in the absorption time of individual transistors in such an inverter are given overvoltage on individual transistors and current surges through them in the switching process. This leads to a decrease in the reliability of the inverter, an increase in dynamic losses (decrease in efficiency), and prevents the increase in the operating frequency of the inverter. The aim of the invention is to increase the reliability of the inverter. The goal is achieved by the fact that in a transistor inverter containing at least one half-bridge with -N-series-connected transistors, shunt by 1 opposite-connected diodes in each arm, the output transformer, the additional windings of which are connected to the input N-1, rectifiers The outputs of which are bridged by capacitors and connected to the connection points of the transistors in the half-bridge arms, and the control pulse drivers connected to the input circuit of each transistor, the outputs of these rectifiers are connected to transparently in series to form a chain with two extreme and N-2 intermediate leads, with the first output of the rectifier chain connected to the connection point of both the first and second transistors in the First shoulder of the half bridge, the last output of this chain is connected to the connection point of the last and the second to last transistors in the second shoulder half-bridge, each intermediate K-th output of this chain is connected through diodes to the connection point of the transistors with the number K + 1 and K + 2 of the first arm and the connection point of the transistors with the number K and K + 1 of the second shoulder, The output of the pulse driver of each, except for the last, transistor of the first shoulder is connected to the locking input of the pulse former of a subsequent transistor through the input delay element, while the output of the driver of each pulse, except the first, of the second transistor, is connected to the locking input of the pulse former of the previous transistor through the input element delay, and the output of the pulse former of the last transistor of the first shoulder and the first transistor of the second shoulder is connected through the input element delay ment. with unlocking inputs of drivers of all other transistors. the ditch of the second and first shoulders, respectively. These delay elements can be made adjustable. Figure 1 shows the circuit diagram of the proposed inverter in the case of a series connection of four transistors in a circuit; Figure 2 shows the current voltage diagrams, pb sn to qie its work. The inverter contains the first and second half-bridge shoulders with series-connected transistors S and 5-8, a capacitive voltage divider on capacitors 9 and 10. The diagonal of the bridge includes the primary winding 11 of the power transformer 12. A load 13 is connected to the secondary winding of the transformer. Transformer 12 has additional windings 14-16, to which the inputs of rectifiers 17-19 with capacitors 20-22 at the outputs are connected. The outputs of the rectifier shafts 17-18 are connected in series according to and form a series circuit, the extreme terminals of which are connected to common points of transistors 1, 2 and 7 ,, 8 and through diodes 23 and 24 to the poles of the main power source 25. The first intermediate output of the circuit The rectifiers through diodes 26 and 27 are connected to common points of transistors 2, Z5, b. The second intermediate output of the rectifier circuit through diodes 28 and 29 is connected to the common points of the transistors 3, 4 and 6, 7. Moreover, between the common points of the transistors connected to one output of the rectifier circuit, always three transistors are turned on, for example, transistors 3, 4 , 5 and 4, 5, 6. The control unit 30 contains control pulse drivers -31-38 for each transistor. The drivers have inputs for the lock signal and the unlock signal for the transistors. In each chain of transistors, the output of each driver, beginning with the driver, closest to the power supply pole (from drivers 31 and 38, respectively), is connected to the locking input of the next driver through delay element 39-44. The output of the last driver of one arm (drivers 34 and 35) through the delay element 45 or 46 is connected to all unlocking inputs of the drivers of the other, googoy shoulder. The locking input 47 of the driver 31 is the input for the lock signal of the chain of transistors 1-4. Shaper's 48 input is the input to the lock signal of the transistor chain 5-8. Diodes 4954 are connected in parallel to the transistors to provide operation at an active-inductive load. Resistors 55-58 improve the distribution of the voltage across the transistors. The inverter works as follows. The number of turns of the additional windings 14-16 is selected in such a way that the output voltage is each. The rectifier and gj ,, f, p were equal to Un 14, where Ufi is the voltage of the power supply 25. Let the transistors 1-4 open in the initial state and the transistors 5-8 closed, which corresponds to the interval (t (j, n ) in Fig. 2. At this interval, the potential Up of the output terminal (the common point of connection of two transistor circuits) is close to Un / the primary current of the transformer -frp current rises, the voltage of C-Ud on transistors 1-4 is close to zero. , 28, 24 are closed, as the voltage from the capacitor 20 is applied to the first one, from the capacitors 20 and 21 to the second, and to the third application APU - 3Uej, inp. To the collector of transistor 6 through the diode 27, the potential Ufj –Ug is supplied (, inp, to the collector of transistor 7 through the diode 20 - potential l) f, - ,,, to the collector of transistor 8 - potential Urj- 3Ue , t,. Thus, at this voltage range, the collector emitter of ultrasonic and transistors 5-8 are determined by the voltages at the output of the auxiliary rectifiers and are equal. At some instant, a lock signal is applied to the input 47 of the driver 31, then through the delay element to the locking the input of the driver 32, etc. At the same time, the locking signals to the base of the transistor s 1-4 are provided alternately, starting with the transistor 1. The feed blanking signal delay quantity for the next transistor is selected larger than the resorption time of the previous transistor. Some time after the signal is sent to input 47 (after the absorption time elapses) at time i, you lock the transistor I. At the next interval (C t4), transistors 2-4 are open, the other transistors are closed. The current starts to fail in the circuit: transistors 2-4, capacitors 20-22, diode 24. The output terminal has potential Up -3Ug {, ffl The un-voltage applied to the transistor 1 is applied, the voltage across the transistor 8 drops to zero as diode 24 opens. Diodes 26 and 28 are still closed. The collectors of the transistors 5, b and 7 through the open diodes 27 and 29 are applied to the potential of the outputs of the rectifier circuit. The collector potential of transistor 5 is 3Uef ,, np, transistor 6 is 2Ug, np, transistor 7 is Ug {, inp. Thus, in this interval, the voltage across all transistors is Ufj / 4.

At time ij, transistor 2 locks up. At the next interval (trj / O, transistors 3 and 4 remain open. Dismid 26 opens, diode 27 closes and closes along the circuit: transistor 3 and 4, diode 26, capacitors 21 and 22, diode 24. Output the output has the potential Up ivypr to the switched off transistor 1 applied voltage un -% binf. to transistor 2 - voltage, (right from capacitor 20. The voltage on the collector of transistor 8 is still close to zero, the collector potential of transistor 7 is equal to ((, schr, so the collector-emitter voltage of transistor 7 is equal to Uq / 4., The total voltage across the transistors 5 and 6 Uj + and also equal to Ir / d., And in general the voltage on the closed transistors does not exceed 1/4 /. At the moment t, the transistor is locked

3. In the next interval (t5tt4, only one transistor remains open 4. The current is closed across, / the circuit of transistor 4, diode 28, capacitor 22, diode 24. The output terminal has potential Up-Ug (, ir, p, to collector: Transistor 2 is applied potential Ziv ,, to collector 3 - 2Ug (,, f, p, so the voltage on closed transistors 1-3 does not exceed Of, 4 The total voltage on closed transistors 5-7U5 + Uf, + U7 Uj, t ,, np , the voltage on the transistor 8 is close to zero. At time t, the last transistor 4 is locked and all the transistors of the other chain 5-8 are turned on at the same time, the elements ki 45 and 46 thus prevent the occurrence of through currents. The processes in scheme .protekayut similarly described hereinafter..

In the TOKa-f p curve in FIG. 2, there are oscillatory pulses of charge current of capacitors 20-22 ..

The delay elements 39-41 and 42-44 can be made adjustable. In this case, it is possible to control the output voltage of the inverter.

In accordance with the stated principles, other inverter circuits can be constructed. For example, a single phase gvk circuit of an inverter will have four pairwise connected chains, each of N-series-connected transistors, and a corresponding two successive circuits of the rectifier

The proposed inverter has a higher reliability than the known one, since it eliminated overvoltages on individual transistors and current surges through them in switching processes. In addition, the new construction of the circuit reduces the dynamic losses in the transistors, increases, other things being equal, the efficiency of the inverter and allows an increase in the operating frequency.

Claims (2)

 1. A transistor inverter containing at least one half-bridge with N-series or transistors shunted counter-on; ocular diodes in each arm, an output transformer, the additional windings of which are connected to the input N-1, straighten the plugs, the outputs of which are bridged-by capacitors and connected to the junction points of the transistor in the half-bridge shoulders, and control pulse drivers included in the input circuit of each transistor, characterized in that, in order to increase reliability, the outputs indicated in the terminals are connected in series, forming a chain with two extreme and N-2 intermediate leads, the first output of the rectifier chain is connected to the connection point of the first and second transistors in the first shoulder of the half-bridge, the last output from the Chain is connected to the connection point of the last and the last but one transistors in the second half-bridge shoulder, each intermediate K-th output of this chain. connected via diodes to the point of connection of the transistors with the number K + 1 and K + 2 of the first shoulder and the point of connection of the transistors with the number K and K-And the second shoulder, while the output of the pulse former of each, except the last, transistor of the first shoulder the pulses of the subsequent transistor through the input of the delay element, while the output of the pulse shaper of each, except the first, transistor. the second arm is connected to the locking input of the former impulses of the previous transistor through the input delay element, and the output is formed. t-al pulses of the last transistor of the first shoulder and the first transistor of the second shoulder are connected through the input delay element to the unlocking inputs of the formers of all the other transistors of the second and first shoulder, respectively. 2. The inverter according to claim 1, characterized in that said delay elements are adjustable. Sources of information taken into account in the examination 1. Authors certificate of the USSR 641613, cl. H.02 M 7/537, 1977. 2, USSR Author's Certificate No. 610269, cl. H 02 M 7/537, 1977, 2