SU842914A1 - Linear interpolator - Google Patents

Description

(54) LINEAR INTERPOLATOR

one

The invention relates to an information-measuring technique and can be used where it is necessary to restore the signal from its samples, for example, in telemetry, communication systems and control.

An interpolating device is known, which is a digital-to-analog converter, the input of which receives the code of the next reading, i.e., the zero interpolation 1 is used.

Such a device has a very low efficiency, since the frequency of the signal ds should be very high.

The closest to the present invention is a linear interpolator containing a serially connected first memory block, an adder, a key, a second memory block and a first integrator, the second input of which and the controlled key input are connected to a clock source, a successively connected reference source, the second the integrator and the third memory block, the output of which is connected to the third input of the first integrator, the fourth input of which is connected to the inputs of the First memory block, adder and interpolator; the second inputs are second The integrator and the third memory block are connected to the source of clock pulses 2.

The disadvantage of this device is low noise immunity, since the device restores the analog signal without correcting faults, which can distort the input samples.

The purpose of the invention is to increase the noise immunity of the linear interpolator.

The goal is achieved by the fact that.) Into a linear interpolator containing the first memory block, the adder, the key, the second memory block and the integrator connected in series, the information input to which is combined with the information inputs of the adder and the first memory block and connected to the input of the linear interpolator, the integrator output is connected to the output of the linear interpolator, the clock inputs of the first key memory block and the integrator are combined and connected to the output of the clock source, a subtraction block is entered, equals, multiplication unit, quad, peak detector and reversible counter, inputs of the subtraction unit are connected respectively to the input and

the output of the linear interpolator, the output to the first inputs of the comparison unit and the peak detector, the output of which is connected to the first input of the multiplication unit, the output of the multiplication unit is connected to the second input of the comparison unit, the first output of which is connected to the combined first input of the reversible counter and the control inputs of the first the memory block, the second memory block and the integrator, the second output — with the second input of the reversible counter, the first output of which is connected to the second input of the peak detector, and the second outputs — via a square p with the second input of the multiplication block.

Due to this, the device compares the incoming new sample with the extrapolated signal value (integrator input), and if their difference is greater than the level of failure detection (at the output of the multiplication unit), then this sample is discarded. Interpolation during the rejection of the reference is carried out with a slope proportional to the voltage at the output of the second memory block memorized at the previous clock cycle. In this way, the correction of failures is carried out.

The drawing shows the block diagram of the proposed linear interpolator.

The linear interpolator contains the first memory block 1, an adder 2, a key 3, a second memory block 4, an integrator 5, a block 6. subtraction, a block 7 of comparison, a reversible counter 8, a peak detector 9, a block 10 multiplying, a quad 11 and a source 12 sync signals.

The first memory unit 1 is intended for storing and storing one of the input signals, and the time of storing coincides with the trailing edge of the sync pulse at the control input. In block 1, the signal from the first (second) inputs is memorized, if the signal at the control input is “O (“ 1) ”.

Adder 2 is designed to calculate the difference of its input signals.

Key 3 serves to transmit its input voltage to the output when there is a single signal at the control input.

Memorization corresponds to the leading edge of the control pulse, i.e. the transition.

The integrator 5 is designed to integrate its input signal with a constant time equal to the duration of the approximation interval Td. The initial conditions from the second input in the integrator are set by applying the signal "1 to the second control input" at the signal "O" at the first control input. The integrator 5 may be implemented on the basis of an operational amplifier, a memory capacitor, and two analog switches.

Comparison unit 7 is designed to compare the input signal modules and form the signal "1 (" O) "at its first output if the voltage module at the first input does not exceed (exceeds) the voltage module at the second input. The second output of block 7 is intense to lie.

Reversible counter 8 is designed to count the signals “1 at its first input (in the forward direction) and the second input (in the opposite direction). At the second outputs of the counter 8, the counting result code (n) is formed, and at the first output, the signal "1 if the counter is in the initial state, corresponding, otherwise" O.

Peak detector 9 serves to detect and store at the output of the module the maximum of the signals arriving at its input, in the presence of the signal "1" at the second control input. Peak detector 9 may be built on the basis of a rectifier and a memory capacitor, which is zeroed at a zero signal at the control input.

The multiplication unit 10 serves to multiply the two input signals and can be constructed on the basis of a digital-to-analog converter, the keys of which are controlled by the output code of the quadrant 11. The quadrant L1 multiplies the input code of the number n by itself. Source 12 clock signals, is designed to form at its output a pulse sequence with a period T.

0 Interpolator works as follows.

The signal samples are fed to the input of an interpolator with a period. The next sample is fed to the inputs of block 1, integrator 5, and block b of subtraction. In block 6 of

 it subtracts the output voltage of the interpolator X (t). The difference (t) - X, (t) in block 7 is compared with the allowable value AX (failure detection level), and if LH | .o, the signal "1 postQ goes to the first input of counter 8, the output code of which decreases by one ( or remains in its original state). At this moment, key 3 is opened (by source pulse 12), and the voltage corresponding to the difference between the peak signal and the previous signal sample is stored in block 4. Once in block 4, the difference between the incoming and previous samples is stored, the zero count in block 1 is recorded. Simultaneously In the integrator 5, a snap reading is set (setting of the initial conditions). Next, integrator 5 will integrate the input voltage in accordance with its value and sign with a constant time G o. Thus, as in the known device 2,

5, the signal is reconstructed from two adjacent samples.

If, then, the signal "1 is formed at the second input of block 7. When the atom, the output code of the counter 8 is increased by

unit, and block 4 records its input voltage upon receipt of a clock pulse. In block 4, the voltage stored previously remains, and this voltage still sets the angle of the piecewise interpolation. In the block, an extrapolated value X (t) is recorded instead of the received count. Thus, when detecting an extrapolation of the recoverable signal is detected, it is realized (mc using the predicted signal.

The level of detectable failures is derived from the following considerations.

The maximum error on the linear extrapolation interval is

n, i (o}

where Ma is the maximum model of the second derivative of the signal.

Then, with n more samples downed

Cm lMi (n + l) 4A7o Z, (n + l) 2

The value of Z. is determined in the detector 9, in which the signal increments are measured by the time To, and the maximum of them, LH, is equal to 2 ,,. Peak detector 9 only works on undisturbed intervals of approximation, since in the presence of failures the control signal from counter 8 (from the second output) prohibits the operation of detector 9. The value (n-1) is calculated in quadrant i 1, at the output of which is the code of the number n + 1. In block 10, a multiplication operation is performed, i.e., the output of block 10 produces a voltage proportional to the level of failure detection.

After the end of the series of downed samples in the interpolator, the voltage level at the output of the CU 10 gradually decreases, i.e. each received readout is accompanied by subtracting 8 units from the counter code.

Thus, in the proposed interpolator, multiple failures are detected, which increases its noise immunity.

Claims (2)

1. “Instruments and systems, control, 1972, No. 11, p. 9-11. 2. USSR author's certificate No. 59669, cl. G 06 F 7/30, 1976 (prototype). / V 7G Y v / i / V