SU840905A1 - Priority device - Google Patents

Description

The device relates to computing technology and is intended for use as a switchboard of a modular (partitioned) memory of multiprocessor computing systems. The processors can also be channels, which in modern computing systems are peripheral processors. A prioritization device is known that allows assigning priorities from a certain Rf-ro to a zero order in descending order. The priority is sampled, starting with a request that has the highest priority and ends with a zero request that has the lowest priority. The highest order request that was last received can exchange priority with another lower request, with the result that the lowest order request is given a temporary priority over the highest order request that was last received by l3. However, the drawback of the device is the sequential servicing of requests, which slows down the overall service time. The closest to the invention in technical essence and the achieved result is a priority device containing decoders, elements AND, OR, NOT, BAN and allowing to provide priority service of exchange requests with the memory block both within one group of requests and between different request groups f2. However, this device also does not provide fast exchange while simultaneously receiving several requests of different priority to different memory blocks, since servicing a higher priority request does not allow processing the request of a lower priority to a free memory block at the same time. The purpose of the invention is to increase speed. The goal is achieved by the fact that, in a priority device containing three decoders, eight AND elements, three OR elements and two BAN elements, the decoder inputs are device code inputs, the first decoder outputs are connected to the first inputs of the first and second elements AND outputs The second decoder is connected to the first inputs of the third and fourth elements AND, the outputs. The third decoder is connected to the first inputs of the fifth and sixth elements AND, the outputs of the first and second elements AND are connected to the inputs of of the element OR, the outputs of the seventh and eighth elements, AND, respectively, form the first and the second {outputs of the device, five three gers and an additional four BAN elements are entered, the device's request inputs are connected to the single inputs of the first, second and third triggers, the first, second The third and fourth control inputs of the device are connected to the inputs of the fourth and fifth triggers, the output of the fourth trigger is connected to the second, inputs of the first, third and. The five elements of And, the output of the fifth trigger is connected to the second inputs of the second, fourth and sixth And elements, the single outputs of the first and third triggers are connected to the third inputs of the first, second, fifth and sixth And elements, the single output of the second triggers A gera is connected to the third inputs of the third and fourth elements AND, the output of the first element I is the third output of the device and connected to the inverse inputs of the first and second elements BAN, the output of the third element AND is connected to the right input the first element a BAN and with inverse input of the third BANNER element, output of the fifth element And soeden with direct inputs of the second and third element BAN, outputs of the second and third element BAN through the seventh element And connected to one input of the second element OR output of the second Element And connected to inverse the inputs of the fourth and fifth BANCH elements, the output of the fourth element I is connected to the direct input of the fourth element BANNER and the inverse input of the sixth element BAN, the output of the sixth element I is connected to the direct inputs of the fifth and w The common BREED elements whose outputs through the eighth element AND are connected to another input of the second OR element, the output of which is connected to the zero input of the third trigger, the outputs of the first and fourth BAN elements are the fourth and fifth outputs of the device and through the third element OR to zero input of the second trigger, and the output of the second element And is the sixth output of the device. FIG. 1 is a block diagram of a system in which the device of FIG. 2 is a block diagram of the device itself. The system contains a priority device 1, processors 2-4, RAM modules 5-6, information bus connection blocks 7 and 8, priority device outputs 9-14, priority device inputs 15-20, information bus connection blocks outputs 21-28, Inputs 29-32 priority devices. , . The priority device contains (Fig. 2) the first element OR 33, the third element OR 34, the second element OR 35, the decoders 36-38, the first-fifth triggers 39-43, the first element I 44, the third .I element 45, the second element is And 46, the second element is And 47, the fourth element is And 48, is the sixth element And 49, the first to the sixth elements BAN 50-55, the seventh 56 and the eighth 57 elements I. (In Fig. 1, for example, three processors and two memory modules). . Priority 1 provides priority information exchange between processors 2-4 and memory modules 5. The connection of the corresponding information buses is made by the control signals of the information bus connection blocks 7-8, to the inputs 9-14 of which the exchange signals from the priority device 1 are generated. The exchange signals are generated based on the request signals received at the inputs 15-17 of the priority 1 device 2-4 processors (with a lower-numbered processor having a higher priority) and a signal to select the required memory module, to inputs 18-20 of priority device 1. .In accordance with one of the exchange signals, On input 9-11, based on requests for inputs 15-20 from processors 2-4, the information bus connection unit 7 provides control signals to outputs 21-23 to the corresponding processors 2-4 and a control signal on output 24 to module 5 memory for the required exchange. Similarly, block 8, based on similar requests on inputs 15-20 and control signals on inputs 12-14, provides communication for exchanging processors 2-4 with one of the signals on inputs 25-27 with memory module 6 via a control signal on input 28 The control signals at inputs 29, 30 indicate the possibility of exchange with the corresponding memory module, and the presence of signals at inputs 31, 32 indicates that the corresponding memory module is currently occupied by the exchange process. The device works as follows . Let the memory modules 5 and 6 be free for exchange at some time, a single signal / sweat is given to the flip-flops 42 and 43. The high-level terminal is fed through the inputs 29, 30. The flip-flop outputs 42, 43 are set to 1 At the same time, two applications are received (requests ) for the exchange of the first processor 2 with the first memory module 5 and the second processor 3 with the second memory module 6. Let us alternately consider the process of satisfying the data of the request; First request corresponds to a single signal at input 15 on trigger 39 and the address of the first memory module supplied to input 18 to the decoder 36 As a result, a single signal arrives at all inputs of the AND unit 44, 1 is formed at its output, which from output 9 is fed to the information bus connection unit 7 and is a control signal for organizing the exchange between processor 2 and memory module 5. At the same time, 1 from the output of the element 44 through the element OR 33 is applied to the zero input of the trigger 39, transferring the status to the zero state and preparing to receive regular requests. In addition, at the moment of the exchange from module 5 to the trigger 42, a signal is given on the input 31, placing it in a locked state for receiving exchange requests with this memory module.

On the second request, a signal is received at input 16 on trigger 40, translating it into a single state. The address of the required memory module from input 19 goes to decoder 37, from the output of which ш is sent 1 to the input of element 48, together with single signals from the outputs of trigger 40 and trigger 43, since the second memory module 6 is free for exchange, and input 30 is fed 1 signal. This causes the triggering of the element AND 48, 1 of whose output enters the input of the BANNER element 53 at the prohibitory input of which there is no single signal, at the output of the BANE 53 element there is 1 initializing signal exchange at the output 13 through the block 8 connecting the information buses between the processor 3 and memory module b. At the same time, through the OR 34 element, the trigger 40 is nullified and prepared for receiving new requests, and the trigger 43 from the memory module 6 receives the input 32 preventing the exchange with this module before the current exchange is completed.

Thus, while simultaneously receiving applications of different priority to different memory modules, the device ensures their simultaneous implementation.

Consider the operation of the device when there are two applications for exchange,

After the exchange with the first memory module 5 is completed, the trigger 42 is fed 1 to the input 29, -c the output of the trigger 42 is fed 1 preparing the operation of the elements 44-46. The first

the request goes to trigger 40 at input 16 and the code of the address of the first memory module, to decoder 37. As a result of these signals, element 45 acts, forming a unit at its output.

The second request corresponds to 1 at the input 17 of the trigger 41 and the code of the address of the memory module on the decoder 38, i.

 which leads to the triggering of the element AND 46, the output of which appears 1, Consequently, at the outputs of the element And 45 and the element And 46 there appear single signals. But, since the simultaneous access of two processors to a single memory module is impossible, the power of a processor with a higher priority is preferred. The solution to this conflict is as follows. A single signal from the output of the element I45 is fed to the input of the element BANGE 50, at the prohibitory input of which 1 is absent, a control signal is generated at the output 10, providing service for the first request,

From the output of the element 46 and at the same time, 1 is banned from the prohibition 51 and 52. At the prohibiting input of the prohibition 51, there is no single signal, the output is 1, applied to one of the inputs of the element 56, but the prohibiting input of the prohibiting element 52 1 from the output of the AND 45 element, which does not ensure the presence of a unit at the second input of the AND 56 element, which remains in the closed state, and the second request is not serviced. But this request is not lost, and upon completion of the first exchange, the second exchange is initialized.

Thus, the device provides priority service to the application while simultaneously pointing to the same memory module,

If during the exchange a request with a higher priority is received to the memory module occupied, the exchange is not interrupted. The newly received request is waiting for the completion of the previous one, the loss of the request does not occur. Schematically this is real: due to the presence of a single signal at zero

5 inputs 31 flip-flops 42 from the memory module for the period of the exchange and, accordingly, the absence of an enable signal at the inputs of the AND 44-46 elements.

0

The device allows, when several orders of different priority are received to different memory modules, to ensure their simultaneous servicing and thereby significantly increase the speed of the device.

Claims (2)

1.Patent of France No. 2301872, cl. G About F 9/18, 1976. 2. USSR author's certificate number 458828, cl. G 06 F 9/18, 1975 (prototype). 1p1 / g.2