SU813728A1 - Frequency multiplier - Google Patents

Description

(54) MULTIPLAYER OF FREQUENCY

The invention relates to automation of measuring and computing equipment, in particular, devices designed to generate a pulse sequence by multiplying and can be used to increase the speed of low-frequency measuring devices when processing frequency sensor signals, to measure the frequency is the simplest method. periods for a calibrated time interval.

A device for multiplying the pulse frequency, which contains two schemes for measuring periods of multiplied frequency, is two seconds. generation of a multiplied pulse sequence and a TLN blocking scheme, the closest in essence to the technical solution to the invention is a device for multiplying the frequency of a pulse sequence, containing a deligel of the reference frequency with a ratio (the division factor K equal to the multiplication factor multiplication, pulse counter, input i. Shapes , pulse counter of the reference frequency, the control unit {and, - logic circuits I. storing register 2.

The disadvantage of this device is the accumulative from period to period} time error of the multiplied frequency pulses relative to the period of the frequency to be multiplied. It is known that a pulse counter can count — the number of pulses is less by one than the actual number of periods. C, in turn, the reference frequency impulse counter forms multiplies of multiplied frequency with a .mueniiiijiii, iM following period, and the Kth named .ibc forms a panbnie ending period; multiplied frequency, which leads to the h; one multiplier frequency error. At; the error accumulates, and after several multiplied frequency iods, the pulse is impulse.,; iii, icM 15, the reference frequency impulse counter and the impu, the first zeroing of the register will be p; c-M1) Lost bf or just the same period, t. E. Prozomet “Sat () G |.

i 1, e, 1i image iii.i - the accuracy –– multiplication of the frequency.

The goal is achieved by heme, which is into a frequency multiplier, containing a reference frequency divider, whose input is connected to the reference frequency bus, and an output to the input of a pulse counter, control, which through the control unit is connected to the input driver, and the information outputs the storage resistor is connected to the information inputs of the pulse counter of the reference frequency, the input of which is connected to the frequency reference bus, is entered by a decoder, a trigger and an OR element, the first input of which is connected to the output of the additional A second bit of the pulse counter, a second input to the first output of the control unit, and an output to the recording information input of the memory register and to the reset inputs of the reference frequency divider and the reference frequency pulse counter, the outputs of which are connected to the decoder inputs, and the first output of the decoder is connected to input recording information counter pulse frequency and to the trigger input, the other input of which is connected to the second output of the descrambler.

The drawing shows the functional diagram of the device.

The circuit contains the shaper 1 of the input signal, the control unit 2, the divider 3 of the support frequency, the element OR 4 ,. the first input of which is connected to the output of the additional discharge of the pulse counter 5, the second input to the first output of the control unit 2, and the output to the information recording input of the storage register 6 and to the reset inputs of the divider 3 and the counter 7 of the reference frequency pulses. The outputs of the counter 7 pulses of the reference frequency are connected to the inputs of the decoder 8, the first output of which is connected to the input recording information of the counter 7 pulses of the reference frequency and to the input of the trigger 9. The other input of the trigger 9 is connected to the second output of the decoder 8.

The device works in the following way.

Upon receipt of each successive multiply-frequency pulse, two pulses are generated in control unit 1, the first of which sets the reference frequency divider 3 to zero, the reference frequency pulse counter 7, operating in the subtraction mode, and rewrites the information from the unit arms of the pulse counter 5 memory register 6. Simultaneously with the setting of the zero position of the counter of 7 pulses of the reference frequency, the decoder 8 generates a pulse corresponding to the zero state of the counter of 7 pulses of the reference It is the second frequency that records the information from the memory register 6 into the counter 7 of the reference frequency pulses and sets the trigger 9 to the zero state 9. The second pulse of the control unit 2 sets the zero counter to the zero state 5 pulses. After a time equal to -

The first counting frequency impulse arrives at the input of the pulse counter 5. During one period of the multiplying frequency pulses following, the pulse counter input 5 enters the frequency pulses.

The frequency reference pulses write off (subtract) the information recorded in the counter 7 of the reference frequency pulses. The pulse frequency at the output of the device is equal to -Krumn

When the pulse count of the reference frequency corresponds to the output pulse duration of at least -f, AR 6 decodes a pulse that sets the trigger 9 to one state, upon further writing off the counter 7 pulses of the reference frequency passes the zero state, and the pulse of the decoders 8 sets the trigger 9 to the zero state and records again information from the storage register 6 into the counter 7 pulses of the reference frequency. During one period multiply. My frequency counter 7

pulses of the reference frequency will form the number of pulses equal to the division ratio of the divider 3 of the reference frequency. Since, due to the quantization error of the pulse counter, the K-th pulse in the period of the multiplied frequency can be generated before the end of the period, to completely eliminate the accumulated error, at the beginning of each period of the multiplying frequency, the counter of the reference frequency pulses is 7, i.e. each period of the frequency being multiplied, exactly K pulses are generated. The pulses of the multiplied frequency from the trigger 9 arrive at the output of the device. In the case of missing or missing multiply frequency pulses, the pulse counter 5 overflows, its additional bit is set to one, and through the OR element it keeps the reference frequency divider 3 in the zero state, the reference frequency pulse counter 7, the decoder and the trigger 9, prohibiting the issuance of multiplied frequency.

Claims (2)

1. USSR author's certificate number 357668, cl. H 03 K 5/01, 1972. 2. USSR author's certificate number 354517, cl. H 03 B 19/00, 1972.