SU789913A1 - Electric signal increasing period time meter - Google Patents

Description

one

This invention relates to electrical measuring technology and can be used in transient time meters.

A digital pulse duration meter is known, containing a transistor key stage, a delay line and a pulse counter U-l.

A disadvantage of this device is the limited range of input signal levels in terms of level and duration.

. The closest to this invention in its technical nature is a digital rise time meter for an electrical signal comprising two sawtooth voltage generators, a comparator, a pulse counter, a pulse generator, and key element 2.

The disadvantage of this device is the limited range of its metrological characteristics (limited speed, reduced measurement accuracy), due to the lower tracking rate, input value compared to the rate of change of this value. The purpose of the invention is to expand the range of values of metrological characteristics.

For this, a digital electric time rise meter, comprising two sawtooth voltage generators, a comparator, a pulse counter, a pulse generator and a key element, an output

10 of which is connected to the input of the pulse counter, the signal input is connected to the output of the pulse generator, the first control input is connected to the input of the first sawtooth voltage generator,

5, a second control input — with a comparator output, the first input of which is connected to the output of the first sawtooth voltage generator — is provided with a decade resistor divider

20 measured signal, reference voltage source, large-scale comparators, NOT elements, AND elements, analog key-measuring comparators, equipotent resistor divider of the reference voltage, two multi-input OR elements, third saw-voltage generator, two-input element OR, coaxial voltage element aJO soani, the second key element

and the second pulse counter, the reset input of which is connected to the output of the two-input element OR, and countable. input - with the output of the second key element, the signal input of which is connected to the generator output impulse; first control input to the input of the first sawtooth generator; second control input to the comparator output, the second input of which is connected to the output of the matching element, the first and second inputs of the connected with the outputs of the second and third sawtooth voltage generators, the start input of the second sawtooth voltage generator is connected to the reset input of the third generator, the first input of the two-input element This OR and the output of the first multi-input element OR, the start input of the third generator is connected to the reset input of the second generator, the second input of the two-input element OR and the output of the second multi-input element OR, whose inputs are connected to the outputs of the measuring comparators with even numbers, the outputs of the comparators with odd numbers are connected to the inputs of the first multi-input element OR, the first inputs of all measuring comparators - to the outputs of an equal-speed divider of the reference voltage, the second combined inputs - to common outputs of analog switches, the first inputs of which are connected to the outputs of the decade splitter of the measured signal and the first inputs of scale comparators, the second inputs of which are connected to the output of the reference voltage source, the first element is NOT connected between the output of the first scale comparator and the input of the first analog switch, the outputs of the second and subsequent elements are NOT connected to the first inputs of the AND elements, the second inputs of which are connected respectively to the outputs of the first and subsequent large-scale comparators, and outputs to the second inputs of analog switches, with the decade divider of the signal under study being switched on between. the input terminal and the common bus of the device, and the equidistant divider of the reference voltage — between the output of the source of the reference voltage and the common; bus device.

. The drawing shows a structural electrical circuit of the device.

 The device consists of an input terminal i, a decade resistor 2 of the measured signal, a source 3 of the reference constant voltage, large-scale comparators 4, elements NOT 5, elements I.6, analog switches 7, measuring comparators 8, an equal-step resistor divider 9 of the reference

voltage, first and second multi input elements OR 10, first, second and third generators 11, 12, 13 sawtooth voltage with start inputs 14 and reset inputs 15, matching element 16, comparator 17, first key element .18, first counter 19 pulses, pulse generator 20, second key element 21, two-, input element OR 22, second counter 23 pulses with reset input 24, - common bus 25.

The device works as follows.

The measured signal is transmitted through decade steps divider 2 to the inputs of large-scale comparators 4. The number of decade steps is selected based on the required number of conditional limits on the level of the input value, and the source voltage 3 is equal to the conventional lower limit. : In the initial state, the key elements 18, 21 are open, the keys 7, except for the key 7 connected to the input terminal 1, are also opened by the zero signals of the comparators 4 and the elements 6. The key l connected to the input terminal 1 is opened by a single signal of the element NOT five . If the level of the signal under study does not exceed the conditional lower limit, during the measurement, the indicated state of the keys 7 remains unchanged, and all measuring comparators 8 are connected to the input terminal 1. When the measured signal exceeds the upper limit of the conventional lower limit, part of the scale comparators 4 start from comparator 4 at the device input, it will work. If p comparators work (p 1,2 ... n, where VI is the number of conditional limits), then the inverted signal p + 1 of the comparator 4 and the single signal of the p-th comparator 4 transmitted through the corresponding element And b, the key closes 7 in the p + 1 th comparator circuit 4, and all measuring comparators 8 will be connected to the p-th stage of divider 2 by one of their inputs. Equal-speed divider 9 forms a constant uniform scale of quantization levels with a single voltage increment at each stage. The quantum value is selected based on the permissible measurement error, and is determined by the inclusion of the corresponding number of steps in the divider 9.

Claims (2)

1. Vgikenina 3. P,, Volkova and. and. Mr. Chadovich And, And. Methods and schemes for the time delay of pulse signals, Moscow, Soviet radio, 1971, p. 114115. 2. Rekhin E.I., Kurashov A.A., and Chernov P.S. Measurement of time intervals in experimental physics, M., Atomizdat, 1967, p. 257-258 (prototype}.