SU763968A1 - Semiconductor read-only memory - Google Patents

Description

The invention relates to computing technology and automation and can be used in digital information processing devices as tabular data, programs, subprograms, code converters, etc. The semiconductor memory device is known, which contains p-type injector transistors with basic Schottky diodes Most A close technical solution to the invention is a semiconductor read-only memory containing address drivers, razrienie razryeniya inverter, elec cients decoder, tran ican matrix and amplifiers schytyvani 2. The disadvantages of these semiconductor permanent storage devices is the low degree of integration, which limits the information capacity of the device. The purpose of the invention is to increase the degree of integration of a semiconductor Permanent Memory. The goal is achieved by the fact that the semiconductor Permanent Memory device contains memory transistors with a p-type injector with Schottky base diodes, the collectors of which are connected to the corresponding outputs of the device, the emitters are connected to the zero potential bus, collectors of second address transistors with a p-type injector, as well as with a collector of a control transistor with a p-type injector, and injectors of transistors are connected Yen to the power rail. The drawing shows an electrical circuit of a semiconductor read-only memory device. A semiconductor permanent memory device contains address first 1 and second 2 transistors with a p-type injector, as well as a control transistor 3 with a p-type injector 4, the base 5 of which and the bases of 6 p-type injector connected to the corresponding inputs 8 of the device, and the first collectors 9 address first transistors 1 with a 7 p-type injector - with bases 10 corresponding address second transistors 2 with a p-type 11 injector, emitters 12 address first transistors 1. with an injector 7 p- type emitters 13 Dresnnyh second transistors 2 with a p-type injector 11 and the emitter 14 of control transistor 3 with a p-type injector 4 are connected to a zero potential bus (not numbered in the drawing), and injectors 4, 7 and 11 to a power supply bus 15, while the second collectors 9 address transistors 1 with an injector 7 are p-type, collectors 16 address transistors 2 with an injector 11 are p-type and the collector 17 of control transistor 3 with an injector 4 are p-type connected to the corresponding cathodes 18 of basic transistor diodes 19 of the storage transistors 20 with injector 21 p-type call Ktorov 22 which soediieny with respective outputs of the device 23 and the emitters 24 - with zero potential bus ppiche 1 injectors 21, 15 are connected to the bus power source.

A semiconductor read-only memory operates as follows.

Device inputs 8 (base 6 address first transistors 1 with a 7 p-type injector and base 5 control transistor 3 with a 4 p-type injector) are given an address code (a combination of low and high voltage signals on the base 6 address first transistors 1 with a p-type 7 injector and a low voltage level on the base 5 of the control transistor 3 with a p-type injector 4). At the same time, high voltage levels are established on the cathodes 18 of the base Schottky diodes 19 of the selected Memory Transistor 20 with the p-type injector 21. As a result, the corresponding word is also read out from the selected storage transistor 20 with a p-type injector 21 on its collectors 22 (device outputs 23, since the same-name collectors 22 of storage transistors 20 with a p-type injector 21 are combined and function as an assembly OR) are high (0.6 0.7 V) voltage levels, if the collectors 22 are open (not connected to the outputs of the device 23). and low (.0, 1B) voltage levels, if the collectors 22 are not open (connected to the outputs of the .23 device), which corresponds to the read word.

Thus, the proposed semiconductor read-only memory, as compared with the known one, is characterized by a high degree of integration, which is ensured by the introduction of memory transistors.

20 with a p-type injector 21 with 19 Schottky base diodes (occupying an area from 1500 μm to 5000 μm and having a speed from 5. not to 15 n) and the fact that the p-type injectors 21 process the power supply not to the memory transistor 20, but also to the corresponding addressed first 1 and second 2 transistors with a p-type injector through the respective basic Schottky diodes 19. it

allows realizing 16 kbps permanent storage device on a 4x4 mm chip.

A semiconductor read-only memory device maintains performance in a wide range of variations in supply voltage ($ 18.) According to the operating current of the injector (1p 1mA), as well as the ambient temperature

0 (-60 ° C T.f + 1250C).

Claims (2)

Invention Formula A semiconductor permanent remembering device containing the control and the first and second address transistors with a p-type injector, the bases of the control and first address transistors with a p-type injector are connected to the corresponding inputs of the device, and the first collectors of the first address transistors with a p-type injector are connected to the bases of the second address transistors with a p-type injector, the emitters of address and control transistors with a p-1 injector; ip are connected to a ground potential zero, characterized in that, in order to increase the degree of integration of the device, it contains ominayuschie transistors with p-type injector with the base of the Schottky diode, whose collectors are connected to respective outputs of the device, emitters - with 5 bus potential of zero, and the cathodes of Schottky diodes - with the corresponding second collectors of the first address and collectors of the second address transistors with a p-type injector, and Q also with a control collector a transistor with a p-type injector, the transistor injectors being connected to the power bus. Information sources, f taken into account in the examination 1. Fursin gi. functional integrated circuits and injection power and active communication on bipolar devices, Microelectronics, vol. 6, issue 2, p. 108-126, 1977. 02. Schetinin U, I., Kramarenko O.L ,, Neklyudov V.A. Monolithic ROM 155РЁ1 with a capacity of 256bit with schema1 from control Sat. Microelectronics and semiconductor devices, vol. 1, Owls. ra5 dio, 1976, p. 50-58 (prototype).