SU752344A1 - Multiprocessor computing system - Google Patents

Description

the arithmetic logic unit is connected to the first input of the register of the application code, the first output of which is connected to the first input of the query generation unit, the first output of which is connected to the first input of the tracking signal generation unit, the output of which is connected to the first input of the output unit, the second input of which connected to the second output of the arithmetic logic unit, the third output of which is connected to the first input of the state signal generation unit, the second input of which is connected to the first output of the receiving unit, in Secondly, the output of which is connected to the first input of the arithmetic unit, the output of the synchronization unit is connected to the second input of the tracking signal generation unit, the second input of the query generation unit and the First input of the priority unit, the output of which is connected to the third input of the tracking signal generation unit, the second output of the query generation unit is connected with the second input of the priority block, the inputs of the synchronization blocks of all processors are the synchronization input of the system, the first inputs of the receive blocks the outputs of the issuing blocks of all processors are the system inputs / outputs of the system, the output of the signal processor of one processor is connected to the corresponding input of the group of inputs of the request processor of other processors, the second input of the processor of the single processor is connected to the corresponding input of the group of inputs of the priority of other processors, A receipt signal generator and a receipt signal comparison unit, the first output of which is connected to the third input of the shaping unit, are inserted into each processor. request, the second output of the application code register is connected to the first input of the receipt signal comparison unit, the second output of which is connected to the second input of the application code register, the third input of the receiving unit is connected to the first input of the receipt signal generator, the output of which is connected to the third input of the forming unit the state signal and the second input of the arithmetic logic unit, the output of the synchronization unit is connected to the second input of the receipt signal generator and the third input of the comparison signal comparison unit, with that the output of the signal the receipt of one processor coupled to a corresponding input of input group of comparison signals receipt of other processors, and a second input receiving one processor unit connected to the output

groups of outputs of the unit for generating signals of other processors, the output of the priority block is connected to the second input of the block in comparison with the receipt signals.

FIG. 1 shows a block diagram of the system and each processor; in fig. 2 - it is possible to implement the structural-logical unit of the formation of the receipt signal; FIG. 3 is a structural-logical block diagram of a comparison of receipt signals.

The multiprocessor computing system contains the li - If processors information line 2, the synchronization input 3, and each processor contains a state synalizer 4, an arithmetic logic unit 5, a synchronization block b, a code 7 of the application, an accompaniment signal formation 8, a block 9 generating the request, priority block 10, receiving blocks, issuing block 12, receipt signal generator 13, receipt signal comparison unit 14.

The receipt signal generating unit 13 consists of an element 15 AND and a driver of a single pulse 16.

Block 14 of the comparison of the receipt signals consists of three-input elements 17 And by the number of devices in the system and the temporary anchor node 1

A multiprocessing computing system works in the following way.

If it is necessary to transfer information from the processor 1, to any processor Ij 1 i | , j 1-p or to some group of processors D; c d ij, 1p, ..., 1, p where D li, l2f ... rln3, with 12, n - 1, and, from block 5 to register 7 of the application code, the code corresponding to the address of the processor, or the code corresponding to the disjunction of the codes of all the addresses of the processors belonging to the group D |.

At the same time, information is received in block 5 from block 5, which is to be transferred to processor Ij or to all processors of group Dc. From the output of the register 7 code of the processor application 1, the code of the application goes to block 9 of this processor

Claims (2)

The group of inputs of block 9 of processor 1 "receives signals of the state of other processors. Block 9 generates a signal for applications only if the processor Ij, or at least one of the processors of the Dz group, is in the Free state, otherwise the signal of the generalized application is not generated until the transition of the processor Ij, or at least of the Single processor from group D, from the Zanto state to Free state, the processor request signal Ij is fed to one of the inputs of block 10 of this processor and to the corresponding input of block 10 of other processors. Similarly, the signals of the application and other processors of the system are triggered, with the time of issuing the request signals and the subsequent operation of the main processor units are tightly synchronized with the clock signals coming from blocks 6, which in turn are connected to the total clock of the entire system 3. Thus, in each re process at the input of block 10, at each time point there is a set of requests from processors awaiting our permission to transmit information. Unit 10 in each processor from the aggregate of requests, taking into account its own request, selects the highest priority request. If the own request is the highest priority, then block 8 receives a signal allowing the processor to transmit information. At the same time, the signal from the output of unit 10 enters unit 14 to the first input of the time reference node 18, and the second input of this node receives a signal from synchronization unit 6. From the first output of the temporary inoculation node, the signal arrives at the first input of the elements And 17 and enables receipt of the receipt signals. From the second output of node 18, the signal enters block 9 of the application and prohibits the formation of the application at the time of transmission of information and waiting for a receipt. According to the signal from block 10, block 8 generates a signal that reads information from block 12 to information line 2. In addition, block 8 generates a tracking signal, which in the case of ne. The transfer of information to the processor C is fed to the corresponding input of this processor, and when information is transmitted to group D of processors, the tracking signal is fed to t inputs of the processors, which correspond to the processors from group D ,,. being in the state of Free Transfer of information to the processors of group D being in the state of the request signal in the state of busy, is produced as they are transferred from the state of busy to the state of free while the process of transferring information is repeated. The corresponding tracking signals in the processors, which are information receivers, carry out the census of information from I trunk 2 to receive blocks 11. At the same time, the signals from the outputs of the blocks 11 are fed to the inputs of the blocks 4 of the generation of state signals and the processors are transferred from the Free state to the Full state. In blocks 11, the reliability of the received information is monitored, for example, by convolving it in absolute value. If the information received by this processor with a failure, then block 11 sends a signal to block 4 and transfers the processor from the busy state to the free state. The acknowledgment signal is not output to the processor, If the information received by this processor without failures, the signals from blocks 11 and 6 are received respectively at the first and second inputs of the AND elements 15, the output of which is fed to the input of the single pulse generator 16, and the block 13 generates a signal receipts. On the receipt signal, information is copied from the reception unit 11 to the arithmetic logic unit 5. The receipt signal is outputted by the unit 13 also to the corresponding system bus. The processor that received the information without failures remains in Zanto state. In the processor that transmitted the information, the receipt signals from all the processors that received the information without fail, go to the block 14 comparing the receipt signals to the second inputs of the And 17 elements, and the third inputs of the And elements receive signals from the corresponding register bits 7 of the application code , at the first inputs of the elements AND there is a permitting signal from the output of the node 18 of the time reference. C, the output of the element And 17 signals are sent to the register / and the initial state of the register 7 is set to the application code when accessing the processor 1 or individual bits of the register 7 corresponding to those processors from group D who received the information without failure. When organizing the next cycle of information transfer in the system, the new processor Ij access to the processors that received the information in the previous cycle, exclude, since the processor Ij or all processors of group D, which received the information, are in the Zan state. They carry out an analysis of the reliability of the received information and the formation of a receipt signal. The exchange of information in the system occurs between other processors in the presence of signals from them a generalized request. If the transfer of information to the processor 1J or a certain number of processors from group D has failed, then the installation of the corresponding bits of register 7 to the initial state will not occur. At the end of the signal- “blocking the formation of the application and a temporary anchor coming from node i8, the if processor will be re-transmitting information. The use of the proposed device makes it possible to eliminate the possibility of receiving invalid information in an arithmetic logic unit at the expense of the hardware organization of the repeated transmission of information, if the previous transmission failed, therefore it allows to expand the functionality of this multiprocessor system, and also increases the productivity her. Claims. A multiprocessing computing system in which each of the prod ucts contains an arithmetic logic unit, a receiving unit, a unit in dachas, a state signal generation unit, a synchronization unit, a tracking signal generation unit, a priority unit, a query generation unit, a code register application the first output of the arithmetic logic unit is connected to the first input of the code register application, the first output of which is connected to the first input of the query generation unit, the first output of which is connected to the first input of the unit φ The signaling of tracking signals, the output of which is connected to the first input of the output unit, the second input of which is connected to the second output of the arithmetic of a logic device, the third output of which is connected to the first input of the state generation unit, the second input of which is connected to the first output the receiving unit whose second output is connected to the first input of the arithmetic logic unit, the output of the synchronization unit is connected to the second input of the tracking signal shaping unit, the second input of the composing unit The axis and the first input of the priority block, the output of which is connected to the third input of the tracking signal generation unit, the second output of the query generation block are connected to the second input of the priority block, the inputs of the synchronization blocks of all processors are the synchronization input of the system, the first inputs of the receive blocks and the outputs of the blocks of all the printers are the system's input-outputs, the output of the signal-generating unit of the state of a single processor is connected to the corresponding input of the group of inputs of the request-forming blocks Oxy processors, a second output of a request processor forming unit is connected to the corresponding input of a group of inputs of a priority block of other processors, characterized in that, in order to increase the reliability of the processed information and increase speed, a receipt signal generator and a signal comparison unit are inserted into each processor the receipt, the first output of which is connected to the third input of the query generation unit, the second output of the application code register is connected to the first input of the signal comparison unit The receipt, the second output of which is connected to the second input of the code register application, the third output of the receiving unit, is connected to the first input of the receipt signal generator, the output of which is connected to the third input of the state signaling unit and the second input of the arithmetic logic unit, the output of the synchronization unit is connected to the second input of the receipt signal generator and the third input of the receipt signal comparison unit; the output of the receipt signal generator of a single processor is connected to the corresponding input the group of inputs of the block of comparison of the receipt signals of other processors, and the second input of the block of reception of one processor is connected to the corresponding output of the group of outputs of the block of formation of tracking signals of other processors, the output of the priority block is connected to the second input of the block of comparison of the receipt signals. Sources of information taken into account at. examination 1. USSR author's certificate number 317064, cl. G 06 F 9/18, 1971. 2. USSR author's certificate number 588900, cl. G 06 F 15/16, 1977 (prototype).