SU746719A1 - Device for reading-out information from storage units - Google Patents

Description

(54) DEVICE FOR READING INFORMATION FROM MEMORY BLOCK

I

The invention relates to memory devices, in particular to permanent memory devices, and can be used in computing and automation.

A long-term memory device is known that contains memory transformers, the output windings of which are connected to the inputs of the read amplifiers; the outputs of the amplifiers are connected to a number register. The device contains coincidence elements and current specifying elements by the number of bits, the current establishing elements are connected to the inputs of the read amplifiers. The device also contains a clock driver. The described inclusion of current-supplying elements improves the speed of the device, but this is accompanied by an increase in equipment 1.

The closest in technical essence to the invention is a device for reading information from blocks of the mi, containing memory transformers with numerical wires, some reading windings of which are connected to the collectors of the first, bases of the second transistors, others to the zero potential of the transistors. The collectors of the transistors of the read amplifiers are connected to the inputs of the number register triggers, the outputs of which are connected to the bases of the respective transistors of the read amplifiers.

The disadvantages of the device include the presence of additional equipment - control transistors 2.

The aim of the invention is to simplify the device.

The goal is achieved by the fact that in a device for reading information from a memory block containing read amplifiers, each of which is made on a transistor, the base of which is connected to the corresponding output of the memory block and the collector to the input of the corresponding trigger of the number register and through a resistor to the voltage source, the setup inputs of the number register triggers are connected to the reset bus, the single outputs of the number register triggers are connected to the emitters of the transistors.

FIG. 1 shows a diagram of a storage device; in fig. 2 - time diagram of the main signals.

The device contains in the memory block rv inductive storage elements 1, and protective shielding with code wires 2 according to the principle “stitched - not stitched. As an example, the firmware is shown by a code probe 2, code 10 ... 1. The windings 3 of the readout of the storage elements I are connected to the bases, transistors 4 of the read amplifiers. The collectors of transistors 4 are connected to the inputs 5 of the flip-flops 6, gated inputs 7 of which are connected to the bus 8, and the installation inputs 9 are connected to the bus 10, Unit outputs 11 from the flip-flops 6 in each bit are connected to the emitters of the transistors 4.

The device works as follows.

The bus 10 connects the setup inputs 9 with a signal 12, which sets the triggers 6 to the zero state in all n bits. At the same time, the single outputs 1 of the flip-flops 6 are set to low (zero) voltage levels, these emitters of the transistors 4 are connected to almost zero potential and the subsequent operation of the transistors 4 is allowed. The signals, which open the transistors 4, are induced by the poles in which the units are flashed, while the signals 15 are installed on the nx collectors, which translate together with the gate signal acting on the bus 8, triggers 6 Noe state. In those bits in which the signal 14 is absent, the triggers 6 remain in the zero state. After the transition of the trigger 6 to a single state, the voltage level at a single output P is set. At the same time high

The level at the output 11 of the transistor 4 is shifted in the opposite direction, and the signal 15 at the collector of the transistor 4 stops. In each bit, trigger 6 is triggered for different periods of time,

determined by the scattering of parameters, specific elements, therefore, if the closing of transistor 4 occurred before the pulse 13 of the interrogation current ended, a surge of 16 is observed at the base of transistor 4. However, this surge does not trigger the transistor 4 because it is locked into the emitter.

Compared to the prototype device, this device has reduced hardware costs by eliminating the control transistors in each bit.

Claims (2)

1. USSR author's certificate number 466553, cl. G II C 17/00, 04.01.74. 2. USSR author's certificate for application number 2545393/24, cl. G 11 C 7/00, 11/21/77 (prototype).