SU736107A1 - Uniform parallel processor - Google Patents

Description

I

The invention relates to the field of computer technology and can be used to create high-performance. dative computing systems for group processing of large data arrays in real time.

Known homogeneous parallel processors, built on the basis of a homogeneous computing environment with a variable structure ji.

Possessing the ability to rebuild the structures of both the processor elements and the computing environment (decisive floor) as a whole, such processors allow more economical than on a traditional structure computer by achieving parallelization of computational processes and are able to show a very high effective speed, calculated in hundreds and more than millions of operations per second.

The closest to the proposed is a homogeneous parallel processor, which is a

The combination of interconnected processor elements with tunable links, controlled by a common control device, is intended for solving problems of group processing of large data arrays in real time. Parallelization of the computational process in this processor is achieved through the use of distributed controls with extensive use of settings and the principle of microprogram control, implemented using local microprogram devices, as well as a software control device. In this case, arrays of microinstructions are stored in permanent memory devices of microprogram devices. Each microcommand specifies a certain state of the processor element, and each array of microcommands represents the microprogram of executing one command (operator), for example, addition, multiplication, division, shift, etc. Then the constant memory should contain arrays, how many commands are contained in the command system of a given processor, and the dimension of the control word (microcommand) in the array is determined by the number of control points of the processor element and the number of accompanying service oh information. At the same time, the same microcommands (microprocessor states) can repeatedly enter different microprograms, so they will be written into the memory of the firmware as many times as they occur in arrays of microinstructions. (microprograms) 21. A significant disadvantage of such a control scheme is that for its realization the need for multiple recording of micro-instructions requires an unnecessarily high amount of permanent memory. The purpose of the invention is to reduce the amount of persistent storage devices required to implement firmware control of a parallel processor. This goal is achieved by the fact that a known homogeneous parallel processor containing a software control unit, l data processing devices, each of which contains an input register, operational register block, output register, AND controllable element block, arithmetic logic unit, and microprogram control unit , the first input of the input register of each data processing device is connected to the corresponding output of the switching unit, and the output of the input register is connected to the first input of the control unit x elements I, the first input — the output of which is connected to the output — the input of the operational register unit; the second input-output of the control unit of the elements I connected to the output — the input of the arithmetic logic unit, the first output of which is connected to the first input of the microprogram control unit, and the second The code of the arithmetic logic unit is connected to the first input of the output register, and the output register output register of each data processing device is connected to the corresponding input of the switching unit, the output of the microprogram control unit The second data processing device is connected to the corresponding input of the software control unit, the first input-output 7 of which is the input-output of the processor, the input of the information receiving unit is the input of the processor, and the output information of the information receiving unit is connected to the first input a switching unit, and the output of the dispatching unit is connected to the control inputs of the information receiving unit, the program control unit and the microprogram control unit of each data processing device; a memory block is inserted, and a constant memory is inserted into each data processing device, the input / output of the permanent memory is connected to the input-output of the microprogram control unit, the first output of the permanent memory is connected to the second input of the input register, the second output the fixed memory is connected to the second input of the controllable element block And, the third output of the fixed memory is connected to the input of the arithmetic logic unit, the fourth output of the permanent memory is connected to the second input of the output register, the second input of the mic block The program control of each data processing device is connected to the corresponding output of the memory block, the input-output of which is connected to the second output-input of the program control block, and the control output of the memory block is connected to the control input of the switching unit. By introducing persistent storage devices, it is possible to avoid repeating the recording of micro-instructions in the memory (takes place in a known processor). In the newly introduced Permanent Memory, an entire set of micro-instructions are recorded, at least in the firmware. In this case, the microinstruction is recorded only once and has its strictly fixed address within the permanent storage. Due to this, it is possible to compile the firmware implementation of the processor commands simply in the form of lists of names of microinstructions with instructions for transition to the next name. Thus, the required set of firmware that implements processor commands is defined on a predetermined set of microinstructions. Firmware compiled in this way, having a more compressed look than similar firmware of a known processor, are stored in a constant

memory device firmware.

The memory block contains a number of different combinations of commands (firmware) that are encountered in this task and set the operating modes of the processing devices in each processor clock cycle. For example, an array string can have the following meaning: the first processing device should perform addition, the second - multiplication, the third - division, etc., and, h4, do nothing. In the next cycle, the combination of commands in the line will be different and, accordingly, the processing devices will already work in other modes. Each combination of instructions for processing devices is written to the memory block once and at the same time receives its address. Due to this, it is possible to compile a problem solving program in the form of a list of various combinations of commands similar to the control at the microinstruction level, and the programs themselves, thus composed, are stored in the operational memory of the program control unit. At the same time, the length of the program commands is also reduced compared with the known processor.

The drawing shows a block diagram of a homogeneous parallel processor built on the basis of four data processing devices (f 4).

The homogeneous parallel processor consists of information receiving unit 1, switching unit 2, scheduling unit 3, memory unit 4 (for example, semi-permanent memory), program control unit 5, data processing devices 6–9 VI, each of which contains an input the register 10, the unit 11 of the controlled elements I, the unit 12 of the operational registers, the arithmetic logic unit 13, the output register 14, the permanent memory 15 and the unit 15 of the microprogram control.

The information receiving unit 1 serves to receive data from outside, temporarily store them and transmit them on commands from the control device to the output of the switching unit.

The switching unit 2 serves to establish the necessary connections between the inputs and codes of the processing devices 6-9, as well as the output of the information receiving unit 1 and the inputs of the processing devices. The desired state of the switching unit is set to

It is generated using information removed from memory block 4 by commands from software control block 5.

Processing devices 6-9 serve to implement elementary computational operations (commands). For example, such operations as

algebraic addition with fixed comma;

0

algebraic addition of floating point numbers;

multiplication of numbers with a fixed

commented;

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multiplying floating point numbers;

dividing fixed-point numbers;

dividing floating point numbers;

0

multiplication of numbers with a fixed comma with an arbitrary format, etc.

Calculations can also be taken as elementary operations.

5 values of functions such as F Ax + B F - AF, + YH

Y A + H, N

These functions are usually found when deciding the composition of algorithms for solving specific classes of problems.

Input register 10 is used to operatively receive data from the input device and from processing devices.

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Output register 14 is used to promptly output results to the inputs of processing devices, as well as to other external users with information.

The arithmetic logic unit 13 directly implements commands, i.e., elementary computational and logical operations.

Block 12 operational registers serves the need arithmetic logic unit.

The unit 11 of the controlled elements I serves to set the pa6otbi modes, i.e., the types of elementary operations performed by the mining devices.

Permanent memory 15 serves to store a variety of micro-instructions. The information in the memory 15 is entered once (for example, in the manufacture of a processing device) and, as a rule, does not change in the future, although this is not excluded.

Firmware control unit 16 serves for storing in the library of the microprograms in its memory and for calling the required microprograms from the library to control their execution. At the end of the execution of the command, a signal is issued to the program control unit. Since the entirety of the firmware may be updated, a portion of the memory for storing the firmware may be on a semi-permanent basis. The memory unit 4 serves to store a plurality of different combinations of instructions on the processing device that are encountered in solving this task. The information in block 4 is recorded before starting the processor to solve the problem. The program control unit 5 serves to implement the program for solving the problem as a whole. Obviously, with the considered method of organizing an account, the program consists in setting rules for alternating the names of the specified combinations of microprograms (let's call them program commands, that is, commands of a higher “level”). Oshgorodny parallel processor operates as follows. The D memory of the dispatching unit 3 is a dispatcher control program that controls the operation of the processor in all modes and situations. A multitude of microinstructions are written once and for all into a fixed memory of 15 processing devices. The program is written in algorithmic language. After translation and assembly, a program is ready for download, containing a full amount of configuration information for all blocks. The settings will be codes for various combinations of commands for block 4 and new firmware that should be added to the existing library of block 16 of firmware control. By solving the task, the assembled program under the control of the dispatcher is loaded into the RAM of the program control unit 5. At the same time, the above-mentioned program settings are loaded into block 4. To solve the task, the dispatcher transfers control to the program control block 5, which starts alternately calling commands from the operating memory of the device (program operators. The called command sends to the local control unit of the block {memory, where it is decrypted and interpreted by a specific combination of commands for processing devices, and then these commands are passed to the firmware control blocks of the corresponding devices. processing programs and the corresponding microprograms implement them. The microprogram control units find out the names of micro-instructions from this microprogram and send them to the permanent memory 15, where they will be interpreted as one of the micro-commands stored there. On the end of the microprogram execution, the microprogram control unit it signals to the program control unit. The program control block executes the next program command and the process repeats. Setting microprograms in the form of various lists of micro-commands over a predetermined set of micro-commands allows you to select a common part of the micro-programs into an independent array of control information, which allows you to reduce the length of the micro-program control words, and therefore significantly reduce the memory required to implement the micro-program management For example, N is the total number of microinstructions; cb-bit microcommand, i.e. the length of the control word; Nv is the total number of commands in the processor instruction set; ti- the number of bits in the microinstruction name in the firmware; obviously UE - p - the average number of microinstructions in the microprogram. The amount of memory required to implement firmware control in a known processor is determined by the expression T., MP. We assume that the amount of memory for the relevant information for both cases is dinak, therefore, the distribution of service information is not included in c. The amount of memory required for re-firmware firmware control of the proposed processor is determined by the formula 1l.-Nv -vNVplg- ,. . When the gain in the memory size is estimated using the expression U Nn -Nvpuog-jjH N-1000, I - 200, 200, ust

m 2ogr2 100O 10, p 50. These data do not contradict the corresponding parameters of modern processors.

Then, substituting this data, we get times. Thus, for this case, the gain is 6 times.

Claims (2)

1. USSR Author's Certificate No. 479114, cl. q O6F 15/00, 1974. 2. Medvedev I. A. and others. Multiprocessor computing systems with a tunable structure. M., 1975 (prototype). ABOUT eight . / sh "and AND / 3 Y6 but