SU734708A1 - Device for effecting quick fourier transformation - Google Patents

Description

one

The invention relates to the field of display technology and can be used in systems and devices for digital information processing as time transducers (XM1 is the sequence of readings of the input signal into the frequency sequence and vice versa.

A device is known that contains a block of RAM, a block of constants,. multiplier of complex numbers, addition unit, subtraction unit, control unit 1

The closest in terms of the tachnic implementation and the functions performed to this invention is a device for realizing a fast Fourier transform comprising a control unit, the outputs of which are connected to the control inputs of the first, subtractor, first, second, third and fourth multipliers, respectively the second and third adders-internat-spruce, the first and second intermediate registers, the address block of constants and the address block of the initial information block, the output of the address block of constants through the block constant This memory is connected to the input of the register of constants, the first, second, third and fourth groups of outputs of which are connected to the first passes of the first third and fourth multipliers, respectively, the outputs of the first, third and second, fourth multipliers are connected to the inputs of the second and third followers The outputs of which are connected respectively to the first and second inputs of the first intermediate register, the output of the addressable source information block is connected to the first input of the random access memory block, The output of which is connected to the input of the first input register, the outputs are connected to the inputs of the first totalizer subtractor, the first and second groups of outputs of which are connected to the second inputs of the first, second and third, fourth multiply, first, second and third groups of outputs of the first totalizer the subtractor is connected respectively to the inputs of the first and second intermediate registers, the outputs of which through the first output register are connected to the second input of the operational memory block LSQ.

A disadvantage of this device is its low speed. The aim of the invention is to increase the speed of e,. The goal is achieved by the fact that the proposed device contains a second input register, the third and fourth intermediate registers, the fourth adder-subtractor and the second output register,, -1 and the second output of the RAM block is connected to the inputs of the third and fourth intermediate registers through the second input register registers, the first and second groups of outputs of the third intermediate register are connected to the third passes of the first, second and third, fourth multipliers, the first and second groups of outputs of the third the weft register and the first group of outputs of the fourth intermediate registers are connected respectively to the first, second and third groups of inputs of the fourth summatorach | {tatel, the fourth and fifth groups of inputs of which are connected respectively to the outputs of the second and third summers-subtractors, outputs of the fourth summer- the subtractor through the second output register is connected to the third input of the RAM unit, the control inputs of the third intermediate register and the fourth totalizer-subtractor are connected to the corresponding outputs them to the control unit. FIG. 1 shows the structural scheme of the proposed USP1 in FIG. 2 is a graph of the Fast Fourier Transform algorithm (FFT) implemented in the device; On fkg 3 - time diagrams of the device; FIG. 4 is a graph showing the percentage of success in device performance for arrays of various lengths. The device circuit includes a control unit 1, an address block of constants 2, a block of permanent memory 3, address block 4, initial information, input registers S, 6, constant register 7, intermediate registers 8-11, sum-subtractor 12, multipliers 13-16, memory block 17,

adders-subtractors 18,19,20, control buses 21-24, output registers 25,26, control rails 27-31,

Claims (2)

The graph of the FFT algorithm (Fig. 2) is shown for an input array of 32 values. The following notation is used in the figure: input sequence indices 32, output sequence indices 33, multiplication by a constant 34, The timing diagram (FIG. 3) shows the sequence of performing multiplication by constants W in prototype (I), the sequence of performing multiplication by W for odd indices of the input sequence (IT), sequence for even indices of the input sequence (TB) the final result (III) is a characteristic feature of the calculation Fourier spectrum analysis is that all the even operands of the original array are processed by an FFT algorithm with a rarefaction in time, and all odd ones by the FFT algorithm with a rarefaction in frequency. Such a partitioning makes it possible to organize the calculation in such a way that during the execution it is possible to combine certain steps in time, for example, in practically the same. equipment simultaneously perform the first iterations for even and non-. even operands. Combining is possible since in this case, for some two-point Fourier transforms for odd operands on the first iteration, no multiplication by constants is required, and for others (for even), such an operation is required. It follows that these iterations can be combined by finding an additional computational resource to perform double the addition of complex numbers. In the proposed device, such a resource is Ludwalled by introducing an additional addition-subtracting unit, in other cases it is possible to do with one such unit, dividing its resource over time that, however, will lead to the complication of communications and, as a result, to a loss in equipment. Consider the operation of the device. The timing diagram characterizing the iteration sequence is shown in FIG. 3, where the following symbols are used; the processing area for the case of the operation of the prototypes I, the processing area of the odd operands W, the processing area of the even, operands 13, the processing area of all operands {V, FIG. 3, by way of example, shows some indications of the degree of constants used at various stages, while the constants have the following form, Z.O & -1, I Г7 i-бА, As can be seen from FIG. 3, when processed simultaneously even and odd values of the source operands are necessary to combine operations in arithmetic devices e, in particular, the following operations are added: (1) a / a (4LL (o -cxJ-c-Cb ,, - b;) SV.t (a ,,) with (2) o, - (a; cb.s) b (as) "1- (-. IV (L.S.P. (3)).) (4) a 4a-kiCb5 4b,) VbJ (((5) o, -b, / (ba,),) (6) (a (,) Sta ,, - s (b, - bJ ts (aa;) ti Cr-b, - ) l (7) a, iS (a, -): C4tS (,) - i cx ,, tS (o, -b,) V, sCa,. bl In the calculation process There are various situations of combining one of operations (1), (2) with operations (3) - (5), as well as combining various personal options of operations (6) and (7) among themselves. For an example illustrating the operation of the device , consider two options for combining operations, the first option: combines operations (1) and (S), the second option: combines operations (6 and (7). First option. Denote the operands for the first combined operation as oi .-. B jOi, leaving unchanged the designation of the second combined operation. At the addresses generated by the key 4, the operands B d and c-v B, respectively, are selected from the operative memory block 11 17, which are then entered into intermediate registers 8, 1 O, Next, the operands and a, 4 ib; and, respectively, are added to the flush registers 9, 11, Accelerating 28, the subtraction addition block is set to perform the first part of operation 1, via bus 31, the second complex-subtracting block is set to the entire operation (5). After that, in block 12, the execution of 1 are operations (5 "j), (bb, ((- in block 20 ((ab,),, (,}. Part of the result of the operation of block 12, and i exactly; () Dd, -1) i) enters multipliers; 13-15, the other inputs of which receive a constant from register 7, where it is received by the memory block 3 at the address generated by the address block 2, multiplication results: (5j - oi c, (added and subtracted at summers 18, 19, which are set to the required operation by bus 29, DA. The result of the last operation is taken to intermediate register 9, The otor accepts operands on the inputs specified in the signal transmitted via the bus 21. The results obtained in blocks 12, 20, hit registers 25, 26, are recorded at the address produced by the address data block 4 in the memory block 17. The second option. After the initial information is recorded in intermediate registers 8-11, the signals tuning the totalizer-subtractors 12,20,18,19 for the necessary operations are received via buses 28, 31, 29, 30, 27 buses and 21 are signals indicating intermediate registers 10, 9 respectively, where you give and where to get information from. Next, in block 12, the following calculations are carried out: (), (, (Oj-Oi) (bj-b), the results {О4.) And (transmitted to intermediate register 8, the results. () And (Lg-b are transmitted to multipliers 13 to 15. From the output of these multipliers, the results o () 5 (b, f b) are fed to the adder-subtractor 18, where, with time separation, b are sequentially generated: 6 (aQ.-a) S (b, ib), S {aj-a,) - v S (bj-b;), which are written into intermediate register 9, Since the multipliers, in addition to the constant input, have two operand passes, a signal is transmitted through bus 22 that instructs the multipliers from each move needed in To the output of the other two multipliers 14, 15, are fed from intermediate register 1O, respectively, operands and b;, from the output of multipliers, the result is So (and Sb, (add up and subtract on time subtractor 19, the results of these operations 3 (,), S) together with the peers from the code of intermediate register 11 are processed on the adder-subtraction body 2. In the two variants considered, all the special features that are encountered in other cases are disclosed. The proposed device FFT has greater speed than known devices. So, for example, in the case of the classical cnfjco6a FFT for the initial array of N complex numbers, N / aCog-NAttceKi is required to perform the calculations, where At is the execution time of the two-point FFT. In the considered case, this time is reduced to (4 / g% 38-2H-) d Csecs, whence the gain in percentage in speed is expressed by the number 7oo / 2eog ti with FIG. 4 shows a graph illustrating gains for various H values. As you can see, it does not exceed 5O% for H 128 values of the input array and asymptotically. decreases with magnification (H. — For the most commonly used value H1O24, the increase is slightly more than 30%, which fully justifies the reduction of the device that followed the implementation of the adopted algorithm. Invention The device for implementing the Fourier transform containing a control unit, the outputs of which are connected to the control inputs of the corresponding first & subtractor, the first, second, third and fourth multipliers, the second and third adder, and the first and second the intermediate registers, the address block of constants and the address block of source information; the output of the address block of constants is connected to the input of the register of constants through the block of permanent memory, the first, second third and fourth groups of outputs of which are connected to the first inputs of the first, second, third and fourth, respectively multipliers, the outputs of the first, third and second, fourth multipliers are connected 7 88 respectively to the inputs of the second and third adders-subtractors, whose codes are connected respectively to the first the second inputs of the first intermediate register, the output of the source information address block is connected to the first V.B. RAM of the RAM block, the first output of which is connected to the input of the first register, whose outputs are connected to the inputs of the first totalizer-subtractor, the first and second groups of outputs of which are connected to The second passes of the first, second and third, fourth multipliers, the first, second and third groups of outputs of the first adder-subtractor are connected respectively to the inputs of the first and second The intermediate intermediate registers, the outputs of which through the first output register are connected to the second drive of the random access memory unit, are characterized in that, in order to increase the speed of the device, it contains the second input register, the third and fourth intermediate registers, the fourth adder-subtractor and the second output register the second output of the RAM block through the second input register is connected to the inputs of the third and fourth intermediate registers, the first and second groups of outputs, and its intermediate register Istra is connected to the third inputs of the first, second and third, fourth multipliers, the first and second groups of outputs of the third intermediate register and the first group of outputs of the fourth intermediate registers are connected respectively to the first, second and third groups of inputs of the fourth adder, the fourth and fourth The fifth group of inputs of which are connected to the outputs of the second and third adders respectively, the outputs of the fourth adder through the second output register are connected etim input operational memory unit, a control guides v.ho- .dy retego intermediate register and the fourth adder-vychitat ate connected to respective outputs of the control unit. Sources of information taken into account during the examination 1. USSR author's certificate No. 421994, class, Q 06 F 15/34, 1974. 2. Foreign electronics, 1973, No. 2, p. 45. t 6 011S2 It08 Fig.Z ucflo dvu) (P P 700 20 I about 16 32 6 W 256 5P 1024 tb d1E2 - wh -about- N Fy