SU668090A1 - Address-access device - Google Patents

Description

The invention of ognosigs to the field of computing technology and can be used in the development of wall-mounted equipment for checking memory storage arrays. A device of address sampling (address switch) is known that contains a binary decoder, which outputs are connected via amplifiers to input buses of coordinate switches ij. However, with the use of many blue decoders in the proposed device, it is difficult to provide the desired current form due to the influence of the parasitic parameters of the device. It is also known an address sampling device containing a binary diode detail encoder, the horizontal buses of which are connected to a pulse voltage source through a switch, and the vertical buses through positive and negative current keys to the corresponding positive and negative GOKT 2 generators. However, in this device, the influence of the parasitic parameters of the circuit is significant. The purpose of the invention is to increase the stability of the shape of current pulses. To do this, an address sampling device contains a binary diode decoder, the horizontal buses of which are connected to the first load terminals and the first terminals of the horizontal switches, and the vertical buses to the first terminals of the vertical switches of the positive and negative currents and through direct diodes to the second terminals the bus and the generators of positive and negative currents of the source of a two-pole pulse voltage are additionally introduced a transformer, the primary winding of which is connected between the bus the source of a bipolar pulse voltage and the second terminals of the horizontal switches, and two secondary windings -. between the second pins of the keys of the positive and negative currents and the buses of the positive and negative currents, respectively.

On retezhe. A schematic diagram of the device is presented.

The device contains a diode-binary decoder 1, a source 2 of a two-pole pulse voltage, horizontal switches 3 connecting the horizontal decoder 1 HbJ with the combined load group 4, keys 5 and 6, made, for example, on reed switches, keys 7 and 8 denying positive and positive currents, generators 9 and 10 negative and positive currents, and a notch transformer 11 with primary winding 12 and secondary 13 and 14. The number of primary windings can be increased and equal to the number of outputs of the pulse voltage source 2 , Horizontal and vertical tires are designated by position 15 and 16.

In the initial state, the keys 3,5,6 are open, and the gates on the keys 7 and 8 are not served.

When a certain load is selected, one of the keys 3 is closed, and the keys 5 and 6 of a certain column according to the decryption.

Then, when a positive (negative) current is formed in the load from source 2, a pulse of negative (positive) coupling appears, which charges the parasitic capacitance of the horizontal bus. The primary winding 12 of the transformer 11, connected in series to the capacitor charge circuit, works as an inductive load (choke), since the key 8 (7) is not yet closed. Naturally, the inductance of the winding 12 is selected within reasonable limits. After the Kan key (7) closes, the load is connected to the generator circuit 10 (9). In this case, the currents through the windings 12 and 14 (13) of the transformer 11 flow the same, and the magnetic fluxes are equal. For symmetrical component currents, the notch transformer does not resist, while at the same time it tends to suppress the effect of asymmetric components of the current.

Thus, the shape of the current in the proposed device depends little on the param- eter parameters and does not change even when using decoders for a significant number of outputs.

Claims (2)

1. USSR author's certificate No. 409371, cl. H 03 K 17/00, 1972. 2. Kalashnikov, V.V., et al. Some issues of the design of two-wire gates of a 2.5D system of high capacity M, MT.VT, 1974, p. 10, fig. 2