SU609170A1 - Device for interlocking quick-action protection of dc plant - Google Patents

Description

one

The invention relates to automatic regulation and relay protection and can be used in the execution of the device for protection of DC installations.

A direct current transformer (TFT) is known. TFT has two saturation droplets with a common control and separate operating windings, a power supply voltage transformer and an intermediate current transformer. The working windings are connected counter-consistently with each other and in series with the secondary winding of the supply transformer. This circuit is connected to the primary winding of an intermediate current transformer, in the secondary circuit of which the TFT load is connected. The half-waves of the alternating secondary current TFT of the trapezoidal shape alternate with the frequency of the supply voltage. The rectified secondary current TFT has dips in the transition region of the alternating rectified current through zero. In order to fill these gaps, not one but two TFTs are installed at the DC power connections, which are connected according to a dual scheme: the supply voltage is supplied from a single power source, but with a phase shift of 90 °, and the rectifier bridge outputs are connected in series with a total load. In the rectified secondary current of the dual TFT, there are no dips. The disadvantage of such a TFT is the appearance of current surges in the secondary circuit during the supply of the supply voltage in the absence of primary current.

A device for blocking a high-speed protection of a direct current installation is known. element {2.

This device is closest to the proposed technical essence and the achieved result.

However, in the case of each pair of chokes flowing in the secondary circuits, saturation of current surges occurred at different points in time (this mode of operation of the dual TFT is possible due to non-simultaneous closing of the switching equipment’s contacts to the supply voltage transformers, or an unfavorable combination of residual inductions in the cores of the chokes ), during the time of simultaneous flow of secondary bypass currents does not occur. The duration of the simultaneous flow of currents can be 5-10 ms, i.e. protection devices having

high speed, falsely triggered.

In addition, when the electronic key is triggered, the TFT bypassed output will maintain a residual voltage equal to the voltage drop at the junctions of the semiconductor key elements. Residual voltage can cause an unacceptably high current to flow at low TFT loads.

The aim of the invention is to improve the reliability of the device by obtaining a signal that blocks the false actions of your devices. The goal is achieved in that the blocking device is additionally equipped with a memory element, the input of which is connected to the output of the time delay element connected to the comparator output, and the output of the memory element is connected to the input of the output element.

The drawing shows a diagram of a device for blocking a high-speed device; it is protected by a direct current device connected to a dual TFT.

The blocking device contains two intermediate current transformers 1, 2 connected to a dual DC transformer 3, a current comparator 4 (voltage), a time delay element 5, a memory element 6, an output element 7.

The input of the time delay element 5 is connected with the output of the comparator 4, to the inputs of which the secondary windings of current transformers 1 and 2 are connected. The output of the time delay element is connected to the input of the memory element 6, the output of which, in turn, is connected to the input of the output element 7. Output element 7 is the output of the blocking device.

With the mutual correspondence of the secondary currents of each pair of cores, the comparator is in the actuated state. In this mode, the output of the comparator has a logical "one" signal. Element 5 is in the unset state and at its output, connected to the input of element 6, there is a logical "zero" signal. Element b also does not work and at its output the "O" signal is held. Element 7, the input of which is connected to the output of element 6, does not give a signal for blocking.

In the mode of occurrence of a current surge in one of the secondary TFT circuits due to a mismatch of the input signals, the comparator returned to its previous state. In this case, with a time delay element 5 is triggered.

and without time delay element 6. Element 7 generates a signal to block devices for which TFT errors in the form of current surges are unacceptable.

If a surge in one of the secondary circuits is followed by a surge in the second circuit, the comparator is triggered, element 5 returns to its previous state, but element 6 returns to its previous state with a time delay, ensuring that signal 7 is present at the input of element 7 "ABOUT. The time delay of element 6 is selected on the basis of the need to time out the mode of the maximum possible duration of the simultaneous flow of surge currents in both secondary circuits of TFTs.

When a direct current of any magnitude flows through the primary TFT circuit, the comparator periodically returns from the actuated state for an insignificant time at the moments of zero crossing of the alternating secondary current of each of the two secondary circuits. In element 5, the input of element 5 in this mode is an intermittent signal “1, but element 5 does not work, since the signal“ O at its input exists for a time not exceeding the time delay of this element. Consequently, the device does not issue a blocking signal.

Claims (2)

1. Belitska MS, Limanov V. A. Transformers of direct current and voltage. M.-L., “Energie, 1964. 2. USSR author's certificate No. 408224, cl. G 01R 19/00, 1973. pn