SU556445A1 - Processor structured for algorithmic language - Google Patents

Description

one

The invention relates to computing and can be used for processing data stored in the operative type, but a program that is also stored in the operative memory.

Processors are known which contain an arithmetic logic unit, a control unit and internal registers. However, in such processors, the representation of the program in machine instructions does not correspond to the representation of this program in an algorithmic language. The sequence of Onertia in machine commands does not coincide with the sequence of operations in the input language.

This is explained by the fact that, on the one hand, any arithmetic expression must be calculated taking into account the priorities of arithmetic operations, and, on the other hand, that the instructions of the programs in the machines listed above are executed sequentially as they are written. in the body of the program. Therefore, the sequence of commands for an arithmetic expression is constructed in the way this expression is to be calculated, not in the way it is written in the input algorithmic language.

Another problem that confronts modern computer technology is translation. Methods are widely known.

program control of the syntactic correctness of programs written in a high-level language and their transformation into a sequence of machine instructions

able to perceive computers. These control and transformation functions are the main components of their programs. These programs take up large amounts of memory, and their work requires a lot of computer time. In addition, programs written in a high level language, after being translated into machine programs, become too cumbersome, completely unremarkable, and their representation in the input language and, therefore, are not comprehensible to the user.

All this leads to the fact that debugging of these programs in the machine causes serious difficulties, and the main method of debugging

is the method of nrob and error. To improve the efficiency of debugging programs, it is necessary that the working programs in us and the machines directly correspond to the source programs written in high-level textbooks.

A processor is known that provides the function of programming languages of high uro5n. This processor contains buffer devices, an associative memory, an arithmetic logic unit, a device

management It implements a dynamic preparation of data structures starting with any memory bit of arbitrary length; the teams are etiolated in the order of their following, and in accordance with the assigned priorities.

However, it is not possible to assign priorities to all elements of the programming languages. For example, the priority of the “+” sign that stands before “(must be lower than the priority (, and the priority of the“ + sign that stands after “(must be higher than the priority” (.

These difficulties are overcome either with the help of special schemes or with the help of an analyzing firmware, which complicates the hardware and slows down the operation of the computing device.

In addition, only one stack is implemented in the specified processor. This leads to the fact that in one stack you need to store instructions, operands in various formats, as well as addresses of non-transitions and operands, which significantly complicates the organization of the stack and complicates the algorithms of working with it, operation with which is carried out by means of programs or firmware, which slows down the operation of the processor.

For example, consider the AND1 1 operator accessing the Absmax procedure (A, N, M, Yy, I, K). ID Absmaks specifies the address of the procedure. Actual non-temporary A, N, M, Yy, I, K in the general case can be expressions, array identifiers, switch identifiers and procedure identifiers. When calculating them, the stack should contain either the calculated values of the actual parameters (in the case of transferring them to the extraction procedure) or the calculated addresses (in the case of transferring them by name). After calculating all the actual parameters, the control must be transferred to the address corresponding to the identifier Absmax. If you store the address of the procedure in the same stack where the calculated actual parameters are stored, then it becomes difficult to find it, since the number of actual parameters in the procedure may be different.

Of the known processors, the closest in technical essence to the invention is a processor containing a control device connected by two-way communications with a register block and an arithmetic-logic device, the first information inputs of which are connected to the information input of the processor, the address and first information outputs - respectively the address and information outputs of the processor, the second information input and output of the arithmetic-logical device are connected respectively to the second information by the output and the second information input of the register block.

In addition, the microprocessor includes a stack memory for temporarily storing data and commands, a device for determining relative priority between two adjacent program commands, and an additional control device, bracket.

However, the stack handling algorithm is complicated in this processor, which significantly reduces performance, the device for determining the relative priority of commands is not universal, since it is impossible to assign priorities to all elements of the programming language. Because of this, in particular, the processor does not have the hardware to implement many algorithmic language operators (for example, procedure statements). In addition, there is no device for syntactic control of source programs.

The purpose of the invention is to improve performance and improve performance when debugging and syntactically monitoring programs.

This is achieved by the fact that a priority analysis block, a syntax control and transcoding block, a command stack and a data stack connected by two-way communications with a control device are entered into the processor, the first and second inputs of the command and data stacks are connected respectively to the information input of the processor and the second information output of the arithmetic logic unit, address, first time and second outputs, respectively, to the address, information output of the processor and to the second information input y arif.metichesko logic unit inputs nrioritetnyh otnoscheniya analysis unit coupled to corresponding outputs of n registers block command stack.

The presence of hardware data and command stacks allows us to simplify the algorithms for working with stacks and thereby increase the speed.

The presence of the priority analysis block allows the hardware to determine the priority relations between all elements of the programming language and thus save equipment (for example, eliminate the brace control device) and, in combination with the stacks, achieve a direct correspondence between the original programs on the algorithmic language and programs in the machine commands , which directly leads to an increase in the efficiency of debugging programs.

The inclusion of a block of syntactic control and transcoding into the processor and the use of formal methods of syntactic control in its construction allows us to significantly speed up syntactic control and combine it with the input of the program.

FIG. 1 shows the scheme of the proposed processor; in fig. 2 is an example of program execution, where the address of variable A is

in fig. 3 - matrix

designation (5) A,

The priority relationships in the matrix have rows for not all commands, since not all commands can be placed into a stack of commands (for example, such commands are "LA," L,), "; .

The diagram shows information input 1 of the processor, arithmetic logic unit 2, block 3 registers, stack of 4 commands, data stack 5, internal information buses 6, 7, address output 8 and information output 9 of the processor, block 10 for analysis of priority ratios, output lines 11, 12 blocks 3 and 4, control device 13, lines 14-19 of state analysis control, block 20 of syntactic control and transcoding.

The processor works as follows.

By setting the address on the bus connected to output 8, the processor can receive information (input 1) from the outside (for example, from main memory) or output it (output 9).

In block 3 of registers contains the current address of the program.

Exposing it to address output 8, the processor reads the next command, and input 1 sends it to the input register in block 3. The code of the read command on line 11 is sent to the priority relationship analysis unit 10, where it is used to select the column of the priority relationship matrix. This matrix stores priority relations between program elements, priority relations are calculated according to the formal grammar of the language using a special technique. Each element of the matrix can have two values.

 U.

On line 12, from the annotated stack of 4 commands, the code of the upper element of the command stack is received, which in block 10 is used to select the row of the priority relationship matrix. If the read element of the matrix

and has a top team relationship

command stack arrives for execution. When executing such commands by iodation by control unit control 13, blocks 2, 3 and 5 are used.

If the read element of the matrix has

m attitude, then the team read

depending on its code, it is either written to the command stack or it is executed. When executing such commands by the control node of the device 13, blocks 2, 3, 4 and 5 are used.

When running, the starting address of the program is entered into block 3, the stacks are cleared, and the initial limiter code is put on the stack of 4 commands

, -.

Block 20 implements syntactic control and recoding of the input program.

For the construction of this block, formal methods of syntactic control are used, for example, a method that allows a formal description of the language to quickly build compact algorithms of the syntax

control These algorithms are then easily implemented in hardware, for example, as a sequence of micro-instructions. Such an implementation of block 20 allows for syntactic control at high speed and

practically combine it with the input of the original program, i.e., no additional time is required for monitoring.

In addition, the same block recodes each line of the original program in the language into the machine string stored in the machine’s memory so as to preserve the maximum correspondence between them, and also reserves the necessary volumes in memory for storing arrays and variables and

compiles tables of variables to their identifiers. These operations are also performed during input of the source program. When block 20 is running, all other processor nodes are used.

Example. Let the operator A: A + B (C – D) / F be written on the input language, where A. C C. D and F are integer variables equal, respectively, to “5,” 4, “3,” 1 and “2 .

Under the control of block 20, this operator will be converted into a program:

LAA. Load address data in time stack A.

: Assign.

L.4 Load variable A. into the data stack.

+ Fold

LB Load variable B into the data stack.

 Multiply (Open parenthesis

LC Load variable C. into the data stack.

- Subtract

LD Load variable D to the data stack.

) Close the bracket / Split

LF Load P variable into the data stack.

: The end of the operator.

The sequence of this program is shown in FIG. 2

Thus, in the processor, the representation of the program in machine instructions directly corresponds to the representation of the program in an algorithmic language.

The processor has the following advantages.

While maintaining the same speed of program execution as in existing machines, the time required for translating programs from algorithmic language to machine commands, as well as for building a work program with library sub-programs, is reduced. As a result, the total program time is also reduced (i.e., from the start of input to the receipt of results).

There is no need to store programs in an objective form, since the transfer of programs from a form to machine commands and the layout of a working program can be combined with the operation of input / output devices.

It is possible to debug programs directly on the algorithmic language.

The availability of electronic computers (computers) is ensured at the level of interpreting systems from algorithmic languages, but with the speed characteristic of programs translated into machine commands.

The listed advantages will allow to increase the efficiency of computer use, to make them more AVAILABLE for a wide circle of users. To write effective programs, the programmer does not require knowledge of special machine languages, knowledge of a standard algorithmic language is sufficient. Moreover, a computer can be used as a study guide for learning this language, especially when implementing8

scrolling mode, i.e., with synchronous processing of the executable program on the algorithmic language and the results of its operation.

Claims (1)

Invention Formula The processor, structurally oriented to the algorithmic language, contains a device for the device, connected with two-way communication with the register block and the arithmetic-logical device, the first information inputs of which are connected to the information input of the processor, the address and the first information outputs are corresponding to the address center information the outputs of the processor, the second information input and output of the arithmetic logic unit are combined with the second information output and the second information output tm input register unit, characterized in that, with a view to operating speed and the Enhance uluchsheip performance debugging and syntactical control programs entered into it priority analysis block, syntax control and code conversion block, command stack and data stack connected by two-way communication with the control device, the first and second stack inputs The command and control units are connected respectively to the information input of the processor and the second output information and the output of the arithmetic logic unit, address, the first and second outputs - respectively, to the address, information output of the processor, and to the second information input of the arithmetic logic unit, a zipper unit, and a zipper processor; with the corresponding outputs of the register block and command stack.