SU552705A1 - Pulse counting on tmp transistors - Google Patents

Description

at least twice the L / o value, then when the condition

Cz + C4

WITH,

the capacitor 6 is charged to a voltage higher than Lnop.

After the termination of the input trigger pulse, transistor 1 closes and transistor 2 opens, as charged capacitor 6 is connected to its gate. A capacitor 9 is discharged through open transistor 2 and the voltage level is set at the output of the counter. Here, the matching of the resistances of the open transistor 2 and the resistor 3 is chosen such that the capacitor 9 is discharged to a voltage lower than i / nop.

With the arrival of the next pulse at the input 5 of the counter, transistor 1 opens again, capacitor 6 is discharged: and the voltage across the gate of transistor 2 becomes less than the threshold voltage. At the end of the pulse, the transistors 1 and 2 turn out to be closed and the capacitor 9 from the power source 4 through the resistor 3 begins to charge, and a high voltage voltage is established at the output 8 of the counter.

With the arrival of the next trigger pulse, the process repeats.

The minimum operating frequency of the counter is determined by the storage time of the charge on the capacitor 6, and the maximum operating frequency by the recharge time of the storage capacitor 9 through the resistor 3.

Claims (2)

1. Valiev KA and others. Digital integrated circuits for MOSFETs. M., “Owls. radio, 1971, P.263--264. 2. Ilyin V.N. and others. Digital circuits and devices on MIS transistors. M., "Energy, 1975, p. 58-59.