SU551575A1 - Probe for checking digital device circuits - Google Patents

Description

connected to the outputs of the gating units, while the second inputs of the element 2IL-NOT and the second element 2I-NOT are connected to the switch and to one of the terminals of the resistor. The drawing shows a structural electrical circuit of the probe. The probe for checking digital device circuits contains an input terminal 1, a terminal 2, positive sync pulses, a terminal 3 negative sync pulses, output terminals 4 and 5, respectively, of the unit level and zero voltage of the discriminator 6, synchronizer 7, blocks 8 m 9 gating, first element 10 2И-NOT, delay element 11, element 12 2ИЛИ, the second element 13 2И-.НЕ, КЗ - trigger 1 element 15 2ИЛИ-НЕ, switch 16, resistor 17, first element 18 and 19 2И2ИЛИ, display unit 20. The input terminal is connected to the input of the discriminator 6, the output terminal 4 is connected to the first input of the element 10 and the first input of the block 8, the clip 5 with BTOpbnvi input of the element 10 and the first input of the block 9, the second inputs of the blocks 8 and 9 are connected to the output of the synchronizer 7, the output element 10 is connected to the first input of element 12 and the input of element 11, the output of which is connected to the second input of element 12, the output of element 12 is connected to the first input of element 13, and S is the RS ‑ three pin 14, the second input of element 13 is connected to switch 16 and through resistor 17 with power supply terminal , the output of element 13 is connected to T. —the input RS-three is 14, the unit output of which is connected to the first input of element 15, the second input of which is connected to the switch 16 and through the resistor 17 to the power supply terminal, the output of element 15 is connected to the first inputs elements 18 and 19, the second inputs of which are connected to the outputs of elements 18 and 19, respectively, the third inputs of elements 18 and 19 are connected to the outputs of blocks 8 and 9, respectively, the outputs of elements 18 and 19 are connected to the corresponding inputs of block 20, and clamps 2 and 3 with the corresponding inputs synchronize ora 7. Probe works as follows. In the initial state, the clamp 1 has a no-load voltage, and at the output terminals 4 and 5 of the discriminator 6, the levels are logical, the RS-trigger 14 is set to the single position, i.e. at its single output - level -t. When measuring levels O or H, the switch 16 is in the open state, i.e. the voltage of the logic H through the resistor 17 is fed to the input of the element 15, switches it, the output is set to level O. Thus, the influence of the second input of the element 15 is eliminated and the feedback circuit of elements 18 and 19 is buffered. In this case, the measurement of the levels O and similar to the prototype. At clamp 4 of discriminator 6, at the control of a logical O, the level is H, at the clamp of 5 level O, at the control of a logical -i at clip 4, the logical O, at clip 5, the logical And. In the absence of sync pulses 7 at the inputs of its synchronizer, its level is O. Therefore, if there is a logical f or logical O at the input terminal 1, the output M of the gating unit, for example, block 8, is formed, which switches one of the elements 18 and its output is set to a level -f, which, arriving at the corresponding input of block 20, causes the indication lamp to light up to the level being checked. When monitoring pulse signals, the initial state of the probe is as follows: at terminals 4 and 5, levels i, at single output RS of trigger 14, level i, at output of element 15, level O, the feedback circuit of elements 18 and 19 is blocked. When the input terminal 1 of the probe is connected to a controlled point, one of the terminals 4 or 5 is set to the level O. This level switches the element 10 to the unit state. Further, entering through the element 12 to the input of the element 13, this level and level, {entering through the resistor 17 and the switch 16, switch the element 13 to the zero state. The RS flip-flop 14 goes to the zero state, i.e. at its single output, the level O is formed. After the switch 16 is turned into a closed state, the level O is applied to the inputs of the elements 13 and 15, which does it nevo; you can switch 71S - trigger 14 at the input T. The output of element 15 is set to level H, which is nocTjoiaeT at the first inputs of elements 18 and 19. The feedback circuits of elements 18 and 19 are unblocked. When sync pulses arrive at one of the terminals, for example clip2, or at the output of block 8, a signal -i is generated at the input of the discriminator 6 or O, which, when it enters the inputs of element 18, switches it to the unit state. The output level i S of element 18 is sent to its second input and, since the level I is at the first input, the measurement result is remembered. If the monitored signal has an initial level that is outside the empty limits, then at terminals 4 and 5, at the moment of measurement of this level, levels are set (which cause the switching of element 10, element 12, and RS-trigger 14. At output RS - trigger 14 sets the level H, which switches element 15. The output of element 15 sets the level O, which entering the inputs of elements 18 and 19 will block the feedback circuits. Since at this time there are levels O at the outputs of blocks 8 and 9 (sync pulse absent) occurs at putting the element 18 or 19 that remembered the measurement result to the zero state.When subsequently changing the voltage level of the monitored signal to a value corresponding to a logical O or H, for example, switching from a bad logical -1 to a good logical O or when switching from a bad O to logical - trigger 14 does not switch, since element 13 does not switch, at one of its inputs there is already a port level O, At the output of elements 15 there is a constant level O which blocks the reverse circuit with connection elements 18 and 19. Rezultatat measuring element 18 is not stored. If the monitored signal has both levels within acceptable limits, then at any moment on one of the terminals 4 or 5 there is a level O, which does not cause switching of the RS-trigger 14. At the output of element 15 there will always be a level C, which allows the element 18 to remember measurement result. Element 11 is introduced in order to exclude a switch between trigger and trigger 14 when switching a monitored signal from one logical state to another. since at this time due to transients there may be cases of a short-term establishment of levels i at terminals 4 and 5. Thus, the result of measuring the voltage levels of the monitored signal is memorized if both voltage levels of the monitored signal have acceptable values, i.e. The reliability of the control increases. and 3 d b e n u mula A probe for checking the circuits of digital devices, containing a discriminator, a synchronizer, the output of which is connected to the auxiliary inputs of the strapping blocks ;;: "the third inputs of which are connected to the output .. and :. ;: discriminator, and in.cicap-:} block, distinguished by the fact that, in order to increase the reliability of monitoring the pulse signal in the external synchronization mode, two 2INE elements, a delay element, 2IL element, 1 5ggler element 2IL-NOT, are entered into it two elements 2I-2ILI, a resistor and a switch, while the outputs of the discriminator are connected Yeni with the inputs of the first element 2I-NOT, the output of which is connected to the first and through the delay element to the second input of the element 2IL, the output of element 2 OR is connected to the S - input and through the second element 2I-NOT to 1 - input of the trigger, whose single output is connected via the 2ILI-NOT element with the first inputs of the 2I-2ILI elements, the second inputs of which are connected to the outputs of these elements and the inputs of the display units, and the third and fourth inputs of the 2I-2IL elements are connected to the outputs of the gating units, while the second inputs of the 2IL- element NOT and the second element 2I-NOT connected to a switch and to one of the resistor terminals. Sources of information taken into account during the examination: 1. For the UK UK number 1361237. QOllR 19/16, 05. 09. 72g. 2. US patent number 3742351, QOlR 31 / O2, 19. 06. 73 g. - (prototype).

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