SU543176A1 - Device for encoding messages - Google Patents

Description

one

This invention relates to automation and computing.

Devices for encoding symmetric-error-correcting messages such as symbol substitutions are known, which contain a binary shift register, adders and switches 1. However, in many cases of using automatic devices, the probability of damage to various symbols in communication channels is not the same. asymmetrical errors occur. In these cases, the use of known devices is inefficient, since the use of specialized encoders for unbalanced channels leads to an increase in speed and speed of information transfer. The closest technical solution to the invention is a device for encoding messages with single asymmetric error correction, containing a computing unit, the first input of which is connected to the output of the control unit, the input of the control unit is the input of device 2. The powers of the codes implemented by this device are relatively small, and their corrective power is “izk. The device allows building codes that correct only single or two adjacent asymmetrical errors.

The aim of the invention is to increase the reliability of the information. In the device described, this is achieved by the fact that the word bank block, the d-x register, the memory block and the result block are entered into it, the inputs and outputs of the word-bank block, the d-x register and memory block are connected to three outputs and the second, third and fourth inputs of the computing unit, the second output of the memory unit is connected to the fifth input of the computing unit through the result unit, the fourth output of which is the output of the device.

The drawing shows the block diagram of the described device.

It contains a word bank unit 1 for storing code words, a block of 2 d-registers where irreducible –s polynomials are stored, used to represent the final tulle, a block 3 of memory in which the results of vector analysis are recorded. These results are compared with the pre-selected values of the corresponding parameters in block 4 of the result. All coding operations are performed by the computing unit 5, and the operation of the device as a whole is ensured by the control unit 6. The first input of the computing unit 5 is connected to the output of the control unit 6, the input of which is the input of the device. The inputs and outputs of block 1 of a word bank, block 2 d-x registers, block 3 of memory are connected respectively to three outputs and the second, third and fourth inputs

the computing unit 5, the second output of the memory unit 3 through the result unit 4 is connected to the fifth input of the computing unit, the fourth output of which is the output of the device.

The information sequence is fed to the input of the control block 6, the output of which acts on the control input of the computing block 5. The computing block 5 samples the binary vector ... Xn - i, or 1, n divides q (q is the prime number) from the block 1 word bank. Then, in the computing unit 5, the deduction of the Cs expression is determined

2 ... X,. , Xi

i.o

modulo an irreducible polynomial f (x) of degree m and index n, stored in block 2. Here .S runs through integer values from 1 to /, where t is the number of correctable errors and a, is a non-zero element of the field GF (™) , / (sat) 0. The value of the deduction is recorded in memory block 3 and compared with the corresponding value of as previously selected. If, then block 4 issues a command to save the vector x in block I of the word bank and directs it simultaneously to communication, with the same information sequences at the input of the device correspond to equal binary vectors from word bank 1.

Switching from one code vector length to another is performed when the service information control unit 6 enters and enters by changing the values of q, Os and polynomials f (x) in blocks 2 and 4. The switching device is set to the number of correctable errors t by switching on the corresponding the number of values 0S (in the amount of t) in block 4 of the result.

The effectiveness of the invention is provided by the possibility of building codes that correct multiple asymmetric errors;

adaptation to the code length and the number of correctable errors; using more powerful codes on the communication channel.

For the power of the codes synthesized by the device, correcting an arbitrary number t of asymmetric errors, the estimate is valid

on

I L ---,

(“+)

and at 1 i, (p is a prime number),

/ l singleL.i,

| F, (2 "+2 -njin + l),

which exceeds the power of all known codes.

Claims (2)

1. Berlekamp E. Algebraic coding theory. M., Mir, 1973, p. 138, fig. 5, 7. 2. "Mathematical issues of cybernetics and computational techie. Yerevan, Publishing House of the Academy of Sciences of the Armenian SSR, 1970, p. 75, fig. 3 f A