SU497584A1 - Logic cell - Google Patents

Description

one

The invention relates to computing and is intended to build adders for digital computers.

Logic cells are known that contain a load transistor, a gate connected to a source, a bias, a source with a cell output and a drain, the first and second key transistors, whose sources are connected to the drain of the third and fourth cable transistors, respectively, with sources connected to a zero potential bus .

The purpose of the invention is to reduce in the logical cell the area of the substrate, the number of components and the number of external terminals while ensuring operation on a common highway, i.e., simplification of the circuit.

This is achieved by the fact that in the proposed cell between the drains of the third and fourth key transistors an additional key transistor is turned on, the gate of the third key transistor is connected to the gate of the second key transistor, the gates of the first, third, fourth and additional key transistors are connected respectively to the four inputs of the logic cell, substrate The transistors are interconnected and € 0 by the gate of the logic cell.

By connecting the two transistors inside the cell (in the opposite arms of the bridge), a reduction in the number of its leads is achieved. Application in the cell bridge switching MOS transistor, providing in the process of functioning and cell

the flow of current through it either in one or in the opposite direction allows increasing the functionality of the cell and reducing the area of the semiconductor crystal.

If there is a inhibitory potential at the gate input, none of the transistors conducts and does not shun the common highway when combining the outputs of several elements.

FIG. 1 shows a circuit diagram of the proposed logic cell; in fig. 2 is a topological diagram of a basic logic element. Logic cell has common input 1,

inputs 2 and 3 of the shoulders of the bridge, input 4 of the diagonal of the bridge, gate input 5, output 6, active MOS transistors 7-II, load MOS-transres-source 12. The device operates as follows.

With a grounded input 5, the signal at output 6 is zero if the following transistors are connected: 7, 8, or 10, 11, or 7, 9, 11, or 8, 9, 10. Otherwise, the signal at output 6 is equal to source potential

nutrition

For a combination of conductive transistors

7.9, 11 the current through the transistor 9 flows in one direction, and for a combination of transistors

8,9, 10 current through the same transistor flows in the opposite direction. Such a different flow of current through the same transistor is permissible due to the symmetry of the design of the MOS transistor (in the process it is allowed (mutual replacement of the drain to the source).

If there is a positive potential at the input 5 and one of the transistors, e does conduct, and output 6 has the third state in which it is not connected to either the pit or the ground.

This allows the IRIs to perform on the proposed cell circuits of adders to load their bits parallel to the common highway. A zero signal is sent through input 5 only to that adder that is currently working on the trunk.

The topological diagram shows the rational use of the crystal area occupied by a logical cell (transistors are tightly arranged for short interconnects).

Subject invention

A logic cell containing a load transistor, a gate connected to a bias source, a source to a cell output, and ne, pvogo and second key transistors, whose sources are connected

respectively, with the drains of the third and fourth key transistors, the sources connected to the zero potential bus, characterized in that, in order to simplify the logic cell circuit, between the drains

The third and fourth key transistors include an additional key transistor, the gate of the third key transistor is connected to the gate of the second key transistor, the gates of the first, third, fourth

and additional key transistors are connected respectively to the four inputs of the logic cell, the substrate of the transistors are connected to each other and the gate input of the logic cell.

1

Pete