SU486465A1 - Adjustable Pulse Delay - Google Patents

Description

one

The image belongs to radio engineering and can be used in computing devices.

A device of adjustable pulse delay is known, consisting of a pulse / C-relaxator on a single-junction transistor, a thyristor, a key transistor, and a charging current-stabilized transistor.

However, the known device has a narrow control range, no delay of the output pulses relative to the triggering of their signals and a high temperature stability.

The aim of the invention is to expand the range of adjustment of the delay of the output pulses relative to triggering signals and increase the temperature stability of the device.

For this purpose, the charge capacitor of the relaxator under the / keys to the collector of the current-stabilizing transistor, parallel to the capacitor through the diode, is connected the thyristor, the anode of which is connected, to the collector of the key transistor.

The drawing shows a circuit diagram of the device.

The device of adjustable duration pulse delay contains a pulse relaxator on a single junction transistor 1, thyristor 2, a key transistor 3 and a charging current stabilizing transistor 4. The capacitor 5 of the relaxer is connected to the collector of the current TOR to stabilization, stor 4. Parallel to the capacitor 5 through

Diode 6 includes a thyristor 2, the anode of which is connected to the collector of the key transistor, Store 3.

Device input - terminal 7, output - terminal 8.

The device is adjustable pulse delay works as follows.

In the initial state, transistor 3 is saturated, transistor 4 operates in active mode as a DC generator, thyristor 2 and diode 6 are turned on, and one transistor 1 is turned off. The collector current of transistor 4 flows through diude 6 and thyristor 2. Capacitor 5 is charged to a low (residual) voltage.

When fed to the input terminal 7 of the triggering I1 pulse of positive polarity, transistors 3 and 4 are locked. Thyristor 2 is turned off due to a decrease in its anode current. At the end of the input pulse

the capacitor 5 begins to charge linearly collector current of the transistor 4. When the voltage on the capacitor 5 reaches the level of the switching voltage of the junction transistor 1, the transistor

included. The output pulse arising on its base is delayed relative to the trigger pulse. Inte (the time delay of the delay is linearly dependent on the control Gating, applied to terminals 9 and 10. The output pulse turns on the thyristor 2 And transfers the circuit to the initial ss: voltage.

When the circuit of diode 6 and thyristor 2 is blocked, which blocks the emulator of a single junction transistor 1, the charging current can be changed 50-100 times, without disturbing the condition of relaxation in the circuit.

The magnitude of the delay of the output pulse for each trigger can vary by the same number of times.

An increase in the temperature stability of the circuit occurs because the emitter-base voltage of the transistors

3 and 1 4 are included in the opposite direction, which leads to the compensation of their surface maritime drifts.

Subject invention

An adjustable pulse delay device, consisting of a pulse RC-switch on a single-transition transistor, a thyristor, a key transistor and a charging current-stabilizing transistor,

characterized in that, in order to extend the range of controlling the delay of the output pulses relative to the snoring signals and to increase the temperature stability, the charge capacitor of the relaxer is connected to the collector of the current-stabilizing transistor, the capacitor through the diode connected to the collector, the key transistor -but.