SU474806A1 - Firmware device with c-value coding - Google Patents

Description

3

command 4, the decoder 6 and the block 10 of the formation of a sequence of constants, respectively. On channel 11, the code of the address of the next command is non-changed to the command counter 4 when executing forwarding operations and a conditional transition according to the exact match of words. On channel 22 there is an exchange of commands with the machine’s RAM. The following micro-operations can be performed: transfer of a code from the register of the number of RAM and command register; transfer of the first address from the address register included in the command register to the RAM address register, etc.

Decoder 6 is a special firmware decoder that is controlled by the output signals of the operation register triggers included in the command register 5 via channel 12 and the output signals of micro-operation register 7 via channel 15. The purpose of the decoder 6 is to sample the corresponding horizontal bus in matrix 8 but the channel 14. At the same time, the corresponding microinstruction (set of microoperations) is executed.

Register of micro-operations 7 is intended for storing the code executed at any given moment of the order of the microprogram (micro-command), i.e. the code indicating the sovokunnost of the micro-operations currently being executed. The setting on the register of the code of the corresponding micro-command is carried out by a signal coming from the matrix 8 via channel 17.

Matrix 8 usually consists of two matrices, the purpose of which is to develop a complete set of micro-operations that ensure the operation of various devices of the machine. Channel 18 receives microoperations that control the operation of arithmetic device 9. Channel 16 receives a microoperation signal, which increases the state of command counter 4 by one (in the natural order of the commands). The channel 20 receives a micro-operation signal that controls the unit 10 for forming a sequence of constants.

The arithmetic unit 9 is designed to perform arithmetic operations on operand codes that enter the AU via channel 23 from RAM and through channel 21 from the constant sequence generator unit. On channel 19, feedback signals arrive at matrix 8.

The constant sequence formation unit 10 is an automaton with a memory of some special type that does not perform the functions of storage, but forms a constant, unchangeable information in the process of calculating a certain class of tasks. The formation of this information is carried out in certain portions, depending on the method of constructing the unit for forming constants. By its functional purpose, it performs

the functions of the persistent storage device, however, this block of pesetas in itself are distinctive features determined by the method of its construction. These features concern both the circuit differences and operation pins, and the principles of using it in the firmware control device as a whole.

The construction of a unit for forming a sequence of constants of an automaton is based on the following nringen.

A defined sequence of constants is fixed. In this case, the constant with the number “i always follows the constant with the number“ / -j-l. With consistent and

By the size of the formation of constants, both the number of constants and their size are taken into account, as well as the splitting of each constant into separate parts (portions), which are determined in turn by the chosen encoding method.

Depending on the number of constants, their size and the division of each constant into parts, the number of states of the automaton is determined, which in the most general case is equal to the sum of the bits of all constants. The transition of the automaton from the state with the number Ui to the state Ui + i is determined by the transition from one bit of constant (groups of bits) to another (to another group of bits) and from constant to constant.

Thus, each state of the automaton is put in a one-to-one correspondence between a certain bit (group of bits) and the constitution of the automaton from one state to another (neighboring).

provides consistent bitwise (or groups of bits) constants formation.

The operation of the proposed firmware control device is as follows.

Let, for example, it is necessary to add the number stored in the RAM of a machine with a certain constant, which is obtained at the output of the unit 10 for the formation of a sequence of constants. The address of this command was formed on the command counter as a result of the execution of any previous command. On channel 3, the address code of the required command from command counter 4 is transmitted to the RAM address register. This command is read out from the RAM and via channel 22 goes to the command register 5. When using, for example, a three-address command system, the duty cycle of the firmware control device

consists in performing the following sequence of commands. At the AI address, the operand code is read from the RAM and, but channel 23 is transmitted to the required AU register 9. Some initial code is stored at AZ.

states of a unit for forming a sequence of constants (hereinafter referred to as an automaton), the transmission of which over channel 13 to an automaton will lead to the establishment of the automaton in a certain state. As a result of this on

the outputs of the machine will be formed according to