SU451088A1 - Device for calculating the values of polynomials - Google Patents

Description

The invention relates to computing and can be applied, for example, in digital computers (CVMs), but based on large integrated circuits.

A computing device is known for calculating an expression of the form

 + Yn-iX- + ... + 1, +

It contains the control block, the register of onerans, the register of results and the “I.

Calculations using this device of expressions of this type are reduced to the formation of products YiX and to the subsequent, to him their addition (f 1, 2, ...). The formation of the products of the DD is performed by i- 1-fold multiplying the operand X by itself and by the operand Yi.

In specialized digital computers where the principles of software control are not used, it is impossible to calculate expressions of the form + UD1 + YoX ° with the aid of this device, since such digital computers lack commands and, therefore, cannot reduce the calculations to multiple multiplication and addition. In software-controlled digital computers when calculating the UpX + + + expressions. . . + Y + using the specified device, you must execute the multiply command and n times at least n times

the addition command, for which one should go to the memory of the digital computer 2 times. This causes both the additional costs of the equipment needed to store the program of calculations and the additional time spent on accessing the storage device.

The purpose of the invention is to increase the speed of calculating the values of polynomials

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The essence of the invention is that adders and additional registers are entered in it, the number of which is equal to the polynomial, the outputs of the adder Y, (O t p) are connected to the same inputs of the register of the coefficient and the outputs of this register are connected to the same inputs of the adder U (O t p), to which, respectively, are the outputs of the circuits “AND, the first inputs of which are combined and connected to the output of the lower bit of the register of coefficient U1 + 1, the second inputs are connected to the same outputs of the register of the operand, and t The inputs are connected and connected to the corresponding output of the control unit, the low-order output of the EI coefficient register is connected to the high-level input of the result register, the shift inputs of all registers except the operand register are connected to the shift output of the uravleia unit. In the drawing, the image and the proposed device. It contains the register 1 operand X; register 2 operand fo; register 3 intermediate results; adder 4 operands; result register 5; The circuit "AND 6 and the control unit 7. The structure of the proposed device includes the register 1 of the operand X, the register 2 of the operand UO, the registers 3 and the adders 4 of the operands Y, (i-1, 2, ..., p), the register 5 of the result. The outputs of register 1 through the circuit "And 6 are connected to the inputs of the adders 4. In this case, the second inputs of the adders and their outputs are connected respectively to the outputs and inputs of the operand registers Yi. The second inputs of the circuits “AND 6” connected to the inputs of the adder of the ONERAND ;, are connected to the output of the low bit of the register of the operand U +, and the third inputs of all the schemes of “AND 6 are connected to the outputs of the control unit 7. The output of the low order of the register 2 operand of the RO is connected to the input of register 5 of the result. The inputs of the shift registers 2, 3, 5 are connected to the output of the control unit 7. All the operand registers Yi, with the exception of the operand register Ui, have m - | - 1 bits, where m is the number of bits of the operands X and Yi. The ONERAND register has t bits. Consider the operation of the computing device. Let it be necessary to calculate 6-5, i.e. L 5, n 2, U 7, Y 3, PP 6. We will assume that in the initial state the operands X and Yi are in registers 1-3, and in register 5 recorded zero. With the start of operation of the device, the control unit 7 opens the circuits 6 connected to the inputs of the adder of the operand Ug and the low-order bit of the operand YU is added by adding the operand X to the contents of the register Yn-i- Then the control unit 7 opens the circuits 6 connected to the inputs of the onrand accumulator F-r, and the least significant bit of the previously obtained amount controls the addition of the operand X with the contents of the onrand register Yn-z, etc. After completing the addition of the operand X with the contents of all n registers of V operands; a shift of the contents of the register 2, 3 and 5 follows. The shift is made to the right by one bit. At the same time, from the register 2 operands Oud to the register 5 of the result the lower digit of the result is not reduced. Further, the process is repeated (i.e., the second bit of the oneranda, the UE controls the addition of the operand / Y with the contents of the register of the operand Y -1, etc.) until all is formed) t and the bits of the result. For the indicated X, Y, and n values, the computation process can be illustrated by the following state table of device registers, where FSU and OCYi are formated to the contents of the registers of operands Woo

Registers

From the considered example it is clear that with the help of the device it is possible to calculate the expression

UD / + + ... + Y, X + Vo,

where / n. To do this, before starting the calculations, it is necessary to add the U slopes; the registers whose numbers correspond to the indices i, and the remaining n - / registers of nonerans must write zeros. With the device described above, it is also possible to extract the expressions vnda Y- (5 n), for which the operand V is written to the register, whose dead time is 5, and zeros are written to the other registers.

The result register 5 does not necessarily have to have (n +) t bits, since the n + 1 most significant bits of the result can be found (in the register of the operative transducer, there is a memory and 3 bp and a device for calculating the values zeros /;

Nomes of the type V yiA, contained in the control unit (1-0

PIA, register of operands, register of results, schemes “And, characterized in that, in order to increase the speed, it is calculated, adders and additional registers are entered in it, the number of which is equal to the degree of the polynomial, and the outputs of the adder coefficient Y; (O t 5 p) are connected to the same inputs of the register of the coefficient U, - 1, and the outputs of this register are connected to the same inputs of the adder U, - (O t: ha), to which respectively the outputs of the I circuits are connected, the first inputs of which are combined and connected to the output of the lower part of the register of the coefficient Y; + ь the second inputs are connected to the same outputs of the register of the operand, and the third inputs are combined and connected to the corresponding output of the accumulator, the output of the lower bit of the register of the coefficient of the operative index is connected to the input of the higher bit of the register The result of the result, the shift entries of the Bseh registers, except for the Onirand register, are connected to the shift output of the unit by an unravlenn.

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