SU443472A1 - Delay device - Google Patents

Description

one

The proposed delay device relates to the field of technology innovation and can be used in computational engineering, automation, in system auto.matical control and control.

The delay devices contain a trigger on transistors and a time setting ./C-chain, in which the reduction of the recovery time is provided by connecting the common point to the time specifying the RC power through a diode to the collector of one of the transistors of the trigger.

However, in known delay devices, a separate source of voltage is used to provide a capacitor / C-foam charge, which makes the delay device much more complicated. In addition, such a device does not allow to operate in self-oscillatory mode without additional complication of the circuit.

With a view to increasing the reliability and expansion of functional capabilities in the proposed delay device, the bridge circuit is connected to a second diagonal between the common power bus and the collector of the output transistor of the trigger.

The drawing is a diagram of the proposed device.

The delay device contains a trigger, made according to the symmetric scheme on

transistors 1 and 2, connected by emitters to a common power bus, and a bridge time setting circuit consisting of a resistor 3, a capacitor 4 l of resistors 5 and 6 with transistor m 7, the type of conductivity of which is opposite to the type of conduction of the transistors of the trigger, connected to the base-terminal transition to the diagonal of the bridge circuit, and the collector - to the base of the output transistor trigger. The bridge circuit and the key to the second diagonal between the common pinna and the collector of the output transistor of the trigger.

The proposed delay device works as follows.

In the initial state, the transistor 2 is open, the storage capacitor 4 is discharged to a small voltage, the distributor is on the open transistor 2. After the tipping trigger, the transistor 2 is locked, and the voltage on its collector jumps up, simultaneously increases The voltage across the resistor 6 is a voltage divider that locks the transistor 7 securely, providing a charge to the storage capacitor 4 from the power source through resistors 3 and 8.

After the time when the voltage across the capacitor becomes somewhat lower than the voltage divider across the resistor of the voltage divider, transistor 7 starts to open. Negative heating from capacitor 4 opens the transistor 2 and the trigger due to its own feedback and due to feedback Associated with a decrease in the latching voltage of the transistor 7 and an increase in the uncoupling signal from the storage capacitor 4 from the storage capacitor 4, it overturns and returns to its initial state. The capacitor 4 is quickly discharged through the open transistors 2 and 7, after which the circuit regeneration process ends. Key 9 is designed to operate the device in the self-oscillating mode. When the key is closed, the flip-flop is thrown, a high negative potential appears abruptly on the collector of transistor 2, transistor 7 is locked by a negative potential on the resistor 6 of the voltage divider, and the accumulator capacitor 4 starts charging at the 8 c 8 resistor. becomes more negative than the potential of locking up the transistor 7, the latter is opened, and the base of the transistor 2 receives an unlocking negative potential, which leads to an increase in the collector current of transistor 2. The voltage drop across the collector of transistor 2 is transmitted to the base of transistor 7, which opens even more. Such transmission occurs until the collector potential of transistor 2 becomes close to zero. At this point, transistor 7 is fully open and the storage capacitor is discharged mainly through open transistors 2 and 7 to ground. After the capacitor has been discharged, the transistor 2 is lowered by the bias voltage. An increase in potential at its collector leads to the locking of the transistor 7, after which the process is repeated. In the process of charging a capacitor, a pulse height is formed, in the process of discharge a pause. The subject of the invention is a delay device containing a trigger, made according to a symmetric transistor circuit connected by emitters to a common power bus, and a bridge time setting circuit with a transistor whose conductivity type is opposite to the conductivity type of the trigger transistors connected to the bridge-diagonal circuit and the collector - to the base of the output transistor trigger, characterized in that, in order to increase the reliability of work and expand the functionality of the device, the bridge second diagonal circuit is connected between the common power schinoy and collector of output transistor latch.