SU443388A1 - Control device - Google Patents

Description

one

This invention relates to the field of computing.

Control devices for computational machines are known, which contain a buffer block of instructions and hierarchical memory filled with commands with executive addresses in advance. Addressable registers serve as the top level of the hierarchy. The recording of intermediate and final results from them into the main (operational) memory is carried out by exchange write commands.

A disadvantage of the known control devices is that all commands referring to addressable registers are received in the buffer command block. The buffer block is released sequentially and, although different operations are performed by different devices, the next operation will not start until the previous command is selected. For example, an arithmetic operation following an exchange record operation cannot be started until the exchange record is executed or started. If the operands of both operations are in different addressable registers, then the time for which the exchange operation will delay the arithmetic is completely lost. The execution of the exchange record may, in turn, be delayed by other calls to the RAM, sometimes for several cycles. The presence of exchange commands in the buffer command block reduces the number of arithmetic commands in it, which increases the average time they are executed.

The purpose of the invention is to increase the productivity of a computer by reducing just an arithmetic unit and a random access memory.

The essence of the invention is that a buffer block of memory accesses is entered into the device, the input of which is connected via the AND circuit of the first group, the second inputs of which are connected to the first output of the decoder, is connected to the output address of the command register entry, the output of the operation code of which is connected to the first the input of the comparison circuit, the second, third and fourth inputs of which are connected respectively to the outputs of the write address, set blocking and exclusion from the comparison of the buffer command block, the same inputs of which are connected respectively of the outputs of circuits "And the second, third and fourth groups. The first inputs of the circuits “And the second and fourth groups are connected to the second output of the decoder, the first inputs of the circuits“ AND the third group - to the first output of the decoder. The second inputs of the circuits And the second, third and fourth groups are connected respectively to the output of the write address of the command register, to the first and second outputs of the comparison circuit.

the fifth input of which is connected to the output of the instruction register entry address. The first inputs of the circuits “And the fifth and sixth groups are connected to the first output of the result register, the second, third and fourth outputs of which are connected respectively to the second inputs of the circuits“ And the fifth group, second and the third inputs of the schemes “And the sixth group. The first and second inputs of the "Seventh Group" circuits are connected respectively to the first output of the decoder and to the third output of the comparison circuit. The outputs of the “And the sixth and seventh groups” through the “OR” circuits are connected to the single inputs of the corresponding write lock triggers, the zero inputs of which are connected to the outputs of the corresponding And the eighth groups, the first and second inputs of which are connected respectively to the output of the buffer memory access block and with the output of the memory block, the first input of which through the circuits "And the ninth group and the second input through the circuits" and the tenth group are connected respectively to the output of the buffer block of outputs, to the memory and to the outputs of addressable registers The inputs of which are connected to the outputs of the respective circuits “PI of the fifth group, the third inputs of which are connected to the zero outputs of the corresponding write blocking triggers, the unit outputs of which are connected to the second inputs. relevant schemes “And the ninth and tenth groups.

The drawing shows a block diagram of the device.

The proposed device contains triggers of operation code 1 of the command register, triggers of write address 2 of command register, decoder 3, comparison circuit 4, AND 5-8 schemes, triggers of write address 9 of register of buffer memory access block, triggers of write address of buffer register 10 commands, write lock setting trigger 11, deregistration trigger 12, AND circuit 13, memory block 14, result register 15 trigger, write lock trigger 16, readiness trigger 17, result register 18, AND 19-23 circuit , scheme “OR 24, trigger lock record 25 and addressable register 26.

The command register is shown by operation code I triggers and record 2 address triggers. For arithmetic commands, this is the number of the address register to which the result of the operation should be directed. For an exchange entry, this is the number of the address register that should be written to the memory.

In fact, the command register contains all the executive addresses of the command.

The buffer block of memory accesses and the buffer block of commands are each represented by one register. The register of the first buffer is shown by the write address triggers 9, the second buffer by the write address triggers 10, the write lock 11 setting trigger, and the exception from comparison 12 trigger. In addition, both registers contain the remaining addresses

commands and codes of operations that are not shown.

There are one addressable register 26 and one record lock trigger 25. In one state, this trigger prohibits by its zero output recording the register from result 18 to addressable register 26, and the single output allows writing the contents of addressable register 26 to memory block 14.

From the command register, the decoder 3 sends the exchange write commands to the buffer block of memory accesses, the arithmetic commands to the buffer block of commands. The operation code and the address of the register of command registers are supplied to the comparison circuit 4. It also supplies the addresses of the record and the signs of the instruction buffer registers of the arithmetic unit. Thus, the write address of each command received in the command register is compared with the addresses of previous unfulfilled arithmetic commands. If there is no match between the addresses, then, together with the reception of the exchange record command, the record lock trigger in the corresponding addressable register is set to one, i.e., until the contents of the addressable register are overwritten in the memory, writing to it from the arithmetic unit is prohibited. The reset of the write lock trigger to the zero state occurs after receiving the code of the addressable register in the memory. In the absence of matching addresses, the recording of two arithmetic commands during the transfer of a command to the buffer command block does not take any additional action.

If the addresses of the command register entry and the buffer block of the command block match, two situations are possible. First, when there is an exchange-write command on the command register. When it is transmitted to its buffer block, the corresponding register of the write lock is assigned to the corresponding register of the buffer command block. Thus, the command of the exchange - record does not establish in a single state a record lock trigger 25, but transfers this responsibility to the previous arithmetic command with the same address of the record. Only at the moment of transfer of the result of this arithmetic command to the addressable register is the write lock trigger 25 set to one. The exchange record from address register 26 is resolved after the closest of the previous arithmetic instructions in the program with the matching address of the record writes its result to the address register ....

In the second situation in the register, the command is the arithmetic command. During its transfer to the buffer block of commands, the register with which the match occurred is attributed to the exception from comparison attribute. This achieves that of a group of consecutive arithmetic commands with matching write addresses in comparison with the write address of the command register only the last command always participates. The definition of the last command is required for the predictions of the situation, since the last arithmetic command must be assigned by the command of the exchange statement following the group of arithmetic commands with matching addresses.

Subject invention

The control unit containing the command register, the output of the operation code of which is connected to the input of the descrambler, a comparison circuit, a memory block, a buffer instruction block, registers, AND, OR, and triggers, characterized in that, in order to improve the performance of the computing machine, A buffer block of memory accesses is entered into it, the input of which is connected via the “AND first group” circuit, the second inputs of which are connected to the first output of the decoder, is connected to the output of the register address of the commap, the output of the operation code of which is connected to the first input of the circuit we are comparing, the second, third and fourth inputs of which are connected respectively to the outputs of the write address, blocking and excluding the comparison of the buffer command block, the same inputs of which are connected respectively to the outputs of the “And second, third and fourth” circuits, the first inputs of the “And second The fourth group is connected to the second output of the decoder, the first inputs of the “AND third group” circuits are connected to the first output of the decoder.

the second inputs of the circuits "And the second, third and fourth groups are connected respectively to the output of the write address of the command register, the first n second outputs of the comparison circuit, the fifth input of which is connected to the output of the write register write address, the first inputs of the" And the fifth and sixth groups connected to the first output of the result register, the second, third and fourth outputs of which are connected respectively with the second inputs of the circuits "And the fifth group, the second and third inputs of the circuits" And the sixth group, the first and second inputs of the circuits "And the seventh group are connected with Respectively to the first output of the decoder and to the third output of the comparison circuit, the outputs of the circuits "And the sixth and seventh groups through the circuits" OR are connected to the single inputs of the corresponding write lock triggers, the zero inputs of which are keys to

the outputs of the corresponding circuits “And the eighth group, the first and second inputs of which are connected respectively to the output of the buffer memory access block and to the output of the memory block, the first input of which is through the circuits

"Both the ninth group and the second input through the schemes" And the tenth group are connected respectively to the output of the buffer block of memory accesses and to the outputs of addressable registers, whose inputs are connected to the outputs of the corresponding circuits "And the fifth group, the third inputs of which are connected to zero the outputs of the corresponding trigger write triggers, single outputs of which are connected to the second inputs of the respective circuits

“And the ninth and tenth groups.

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