SU424141A1 - DEVICE FOR SORTING INFORMATION - Google Patents

Description

one

The proposal relates to the field of automation and computer technology and is intended for the logical processing of information on the grounds.

Apparatuses for sorting information are known that operate on the principle of ordered sampling using associative memory properties. To search for and select the next sortable character, it is necessary to EXECUTE a large number of elementary logical operations, which takes considerable time and causes the complexity of the device control circuits.

The proposed device is characterized in that the inputs of the circuits "AND of each cell are connected to the first logical input of this cell, the output of the first circuit" AND is connected to the inputs of the circuits "OR. The second inputs of the first and second circuits “OR are connected respectively with the second logic input of the cell and the output of the second circuit“ I. The output of the second OR circuit is connected to the first logical output of the cell, which is connected to the first logical input of the first adjacent cell of the matrix. The output of the second OR circuit is connected to the second logical output of the cell connected to the second logical input of the second adjacent cell of the matrix. The input of the second circuit "And connected via an inverter to the third logic input of the cell, which is connected

with the third logical output of the same top cell, connected to the third logical input of the third adjacent matrix cell. The first inputs of the input circuits And the trigger are connected to the control bus of the corresponding matrix row, and the second inputs are connected respectively to the second logic input of the cell and the output of the inverter. The trigger output is connected to the information input of the cell,

connected to the input of the first circuit "I. This simplifies the device and improves its speed.

Sorting is done by sequentially selecting the maximum attributes, with each view of all the characteristics being sorted being performed in parallel.

Let some memory device having L lines with n binary bits each be stored in an arbitrary order of N l-bit binary characters.

AI - and ;, p, o /, p-1, -, a, y,. -1 og, 1 For definiteness, we can assume that the senior / g-th rank of the criteria is on the left. Any segment of a feature containing / its lower-order bits (/ 1,2, ..., p) is called the / th remainder: 1 feature.

The algorithm in the division of maximum prizpak consists of a trace.

In the first step, the contents of the left (n-th) column of the matrix of storage elements (i.e. the higher bits of the features) are viewed.

If for all the strings lag, "0 or 1,

then, this step does not reduce the number of signs, among which may be maximal, and the next step should check the (n-1) -e bits of all L residues, each of which contains (n-1) bits.

If for some lines O, and for others a, -, 1, then the first are not further considered, and the last constitute the set of lines viewed in the next step.

In the / -OM column, the contents of the / -th column of the storage element matrix 10B are displayed for a selection of rows at the previous step.

If all Oi.j О or all ajj 1, then on the next step all (/ -1) -th residues of the same set are checked.

If, however, uij is only for some rows, then the set allocated for the next step is reduced accordingly.

The set of lines selected on the last (-th) line (in the particular case, the line consists of one line) contains all (equal) maximal signs.

For the hardware implementation of the described algorithm, which is the essence of the invention, it is sufficient to build a combinational logical network that implements the function for each bit uij

./X

X (a ,, V a.jZij “i,; V Z2. (H.jV. V 2; vjV /)

where Zi, j- "input signal of the / th column (pitch) is equal to" 1 for those rows that are included in the set checked on the / -th stitch, zi, i - "output signal of the / -th column (pitch) equal to "1 for those lines that are allocated to check on the PA (/ + 1) th step.

FIG. Figure 1 shows a block diagram of the proposed device (without control lines of the matrix rows); pas figs. 2 is a cell diagram of the proposed device; pas figs. 3 is a cell diagram for the case when the proposed device is executed without combining with the storage of the storage of features.

The device is made in the form of a matrix consisting of N-n identical cells 1.

Each cell has input 2 of variable z, output 3 of variable z, input 4 of variable x, output 5 of variable x, output 6 of variable y, output 7 of variable y /, and information input 8.

Inputs 8 of each cell are connected to the corresponding outputs of the coupling feature storage device.

Each cell contains an inverter 9, schemes "And 10 and 11, schemes" OR 12 and 13, a trigger (or some other storage element) 14 with input circuits "And 15 and 16. Input circuits" And all cells of a given matrix row are connected with the control P1INA 17 of this row of the matrix. The device works as follows. The combination part of each cell implements the functions:

x ha, (2)

y - y, (3)

g: - hectare V Sch / - z (and V у): -: - z () (4)

We give to all inputs 4 upper rows of Xjj - 0 cells. Then, on outputs 5 of the upper row, according to expression (2), we get:

x ,,,. a,.,

a na outputs 5 lower (/ V-th) line:

. ,, ... -. ,/ (five)

Let's connect in all the cells of the bottom line outputs 5 with inputs 6. Then, according to expression (3), at the inputs of 6 all cells of each column we get

U1.1 -Y; i.i-h, i V 22,; a2jV, ..., V2; v.A, / (6)

Now let's go to all the inputs of the left column of the 2, -, cells. Since in each column, according to (4),

z z ()

and y is determined by expression (6), then on the output 3 of each cell, we obtain a function z corresponding to expression (1).

Thus, to select the maximum attribute, you need: on the bottom line

matrix connect all outputs 5 to inputs

6 corresponding cells; all inputs 4

top line apply constant to all

Inputs 2 of the left column - constant “1.

After the termination of the processors, the signal "1 appears at the outputs of the 3 cells of the right column in those rows where the maximum attributes are contained.

In order to continue the sorting (highlighting the next in order of the maximum attribute), it is necessary to exclude already isolated prizpak from consideration. This can be done by replacing them in the storage device with the minimum possible signs "00 ... O.

Another way to exclude selected features is that Zi, –0, is fed to the previously selected lines. This method provides a further acceleration of sorting. Another advantage of this

The method consists in that the information stored in the storage device is not changed during the sorting process.

To perform the sorting by successively extracting the minimum features, it is sufficient for the information input.

each cell instead of the direct signal of the corresponding binary bit to give its inverse. Then, at each step, the maximum inverse feature codes will be allocated, which corresponds to the minimum forward codes.

Combining a sorting device with a storage device for storing features, each cell, in addition to functions (2), (3), (4), also implements the following functions: unit installation

S qx (7)

setting “zero”

R qy (8)

where q is the signal but control bus 17.

This device has three modes of operation: write, read and sort.

When writing "-rush word

X,, Xi I,

which is to be recorded, is fed to the corresponding inputs of the 4 cells of the upper row of the matrix.

The inputs of all 2 cells in the right column of the matrix are given by Zi, i 0.

Using the variable q, the address of the entry is indicated, namely: bus 17 of the line to which the word X is to be written is given 9g 1.

Since all 2 0, then xx, and the word X goes to the second inputs of the “And 15 all rows of the matrix.

Since in the lower row of the matrix, outputs 5 are connected to inputs 6, then the inputs of 6 cells of all lines also contain the values of the corresponding bits of the word X, and therefore, the second inputs of the "And 16 all lines" of the corresponding bits of the word X.

As a result, when a signal q 1 is applied to a certain string, the word X is paraphasically written into the storage elements of this string.

If the word X needs to be written simultaneously in several lines, then it is enough to send a signal q I to all these lines.

The information in any line (or in any set of lines, including a general reset) is reset by recording the word X "00 ... O.

When reading, the reading of the selected (maximum) feature is performed as follows.

The input 2 cells of the left column of the row where the maximum attribute is selected is given a signal z, and the inputs 2 of all the remaining lines are a signal z 0. The inputs 4 of all the cells of the top row are given a signal x Q. Then

according to (2) and (3), at the outputs of 5 cells of the lower row of the matrix (and if there are connections of outputs 5 with inputs 6, this word will also be read at the outputs of 7 cells of the upper line).

If there are several identical maximal signs in the array, then for their separate reading it is necessary to mark all the selected ones (i.e., those containing the maximum

signs) lines, and then read them in turn in an arbitrary fixed order (for example, from top to bottom). Each read is performed as described above. Sorting is done in the same way as

and in the above variant with a foreign storage device.

The proposed device has complete homogeneity (both in terms of the uniformity of the cells, and in the sense of connections between

cells; all connections are made according to the short-range principle). This informs the proposed device all the known positive properties of homogeneous structures (computing environments).

Subject invention

A device for sorting information containing a matrix of cells, each of which consists of a trigger with input circuits "And, inverter, circuits" And and "OR, characterized in that, in order to simplify the device and improve its speed, the inputs of the circuits" li cells are connected with the first logical input of this cell, the output of the first AND circuit is connected to the inputs of the OR circuit, the second inputs of the first and second OR circuit are connected respectively to the second logic input of the cell and

the output of the second circuit "And, the output of the second circuit" OR is connected to the first logical output of the cell connected to the first logic input of the first adjacent cell of the matrix, the output of the second circuit "OR connected

with the second logical output of the cell connected to the second logical input of the second adjacent cell of the matrix, the input of the second circuit "And connected via an inverter to the third logic input of the cell, which is connected

with the third logic output of the same cell, connected to the third logic input of the third adjacent matrix cell, the first inputs of the " And trigger trigger circuits are connected to the control bus corresponding

matrix rows, and the second inputs are connected respectively to the second logic input of the cell and the output of the inverter, the trigger output is connected to the information input of the cell connected to the input of the first “I.

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