SU415819A1 - - Google Patents

Description

one

The invention relates to the field of radio engineering, in particular to systems for the transmission of discrete information.

A first-order Reed-Müller corrective stroke decoding device is known, containing a receiving register, modulo-two adders and “I.

In order to simplify in the proposed decoder, the output of the first bit of the receiving register is connected to one of the inputs of modulo 2 adders, the output of the receiving register with the number corresponding to the expression 2 / + 1 is connected to the other input of each of them (where , 2 ...), and the output of each adder modulo 2 through a serially connected circuit “And, a counter and auxiliary circuits)“ And connected to a common adder, to the auxiliary input of which the output of the receiving register is connected, and the output of the adder via a controlled key By connecting to the input of an additional adder modulo 2, wherein the counter outputs conclusions are respective information symbols, and the control inputs of the main and auxiliary circuits "AND inputs are sootvetstst1Vuyuschih basic pulse sequences.

The drawing represents the proposed majority decoding device of the first-order Reed-Muller correction code.

The significance of code n 8, the number of information symbols and the number of corrected errors g 1-para. Meters of the proposed device.

The device contains a receiver (d / 2-f 1)

bit register I, adders 2 modulo

two, shks:.: s «II 3. three-fold

counters 4, schemes "And 5, controlled

key 6.

The received Reed-Müller code is formed by manipulating the information symbols ao, oi 2 and aa with the pulse sequences Xo, Xt, X2, Az of the form

 one

1 about 1 1

1 1 1 about

1 about 1 a, -.

0o

5, -, O

"COMPANY

eleven

oh oh

25

These sequences are formed in the Reed Müller code coding device and, after a symbolic sum modulo two, through a drop of link, are applied to the And 3 and 5 schemes of the decoding device.

The signal Z is outputted to the -key 6 of the decoder synchronizer to connect the output of the adder 2 to the input of the counter 4, which implements the majority decision for the symbol "0.

The operation of the decoder is carried out as follows.

Before receiving the next codogram of the code, the device is reset to the initial state by the signal "INSTALLATION", which sets all the counters to the position "100 (one in the least significant bit). In this case, the key 6 is open.

In the process of receiving a codogram (in the general case, possibly distorted at one of the positions), we freely enter the input of the receiving register 1. Simultaneously, one of the INPUTS of the diagrams from the encoder is supplied in phase with one of the INPUTS. Therefore, from the summators to the input of three counters 4, information is provided on the presence in the received codogram of pulse sequences carrying information on information symbols Rxi, as, az. If such an IB sequence is available (a;), up to four pulses can be recorded in the counter. If there is an error in the codogram, the number of recorded pulses is three. If there are two errors in the codogram, this code only allows to detect this case (these errors cannot be corrected), and two units are written to the counter.

If, however, the value of ai 0 is transmitted, then the corresponding pulse sequence / Y, is absent in the structure of the codegram, and 1 in the counter, the pulses are not recorded. The conclusion is one or two errors. In this case, one or two units are recorded in the counter, respectively.

The high-order counter stores the value being decoded. If a unit is recorded in the high-order counter, then the decoding nm value is ag 1. This can be when recording three or four pulses (taking into account the initial state of the counter). If the high-order bit of the counter is in the zero state, (if there is one or two errors, the number two can be stored in the counter

or three). In the process of receiving all the characters of the codegram, we perform decoding.

The next step is decoding the value of ao. It is produced at the time preceding the reception of the first character of the next pattern. The key 6 is closed by the signal Z, and the "And" And 5 circuits are applied to the pulse sequences X {, beginning with the fourth signal. Four total cycles of the order are applied to the adder, the pulse sequences Xi, Xz, Xs are controlled by the decoded ones for the first one: n ai, az and az, and the next fourth, fifth, sixth and seventh characters of the codogram from register 1.

From the adder to the counter 4, which implements the decoding of the symbol ao, receives four characters. The majority decoding is carried out as in the other three counters: the information on the value of ao is taken from the most significant bit of the counter.

Subject and d o rn

Majority Decoder

the first-order Reed-Müller Correction Code, containing the receiving () bit register, (K. - modulo 2 adders and "P circuit, characterized in that, in order to simplify the decoding

device, the output of the first bit of the receiving register is connected to one of the inputs of the som.matorov modulo 2, to the other input of each of which is connected the output of the bit of the receiving register with the number corresponding to the expression 2 / + 1 (where / is O, 1, 2 ...), and the output of each adder modulo 2 is connected via a sequentially connected circuit “And, a counter and auxiliary circuit“ And is connected to a common adder, to an additional one (the input of which is connected to the output of the receiving register, and the output of the common adder is connected to additional entry adder modulo 2, wherein the counter outputs are the outputs of the respective information symbols, and the control inputs of the main and auxiliary circuits "and are inputs of the corresponding basic pulse sequences.