SU406225A1 - - Google Patents

Description

MULTIFUNCTIONAL STORAGE DEVICE

one

The acquisition relates to a computing technique.

Multi-functional memory devices that perform arithmetic and logical operations are known. However, their operation does not include logical operations, in which, after each i-th bit of the choo A, the i-th bit of the B number follows.

The purpose of the invention is to expand the functional capabilities of the device.

The proposed device differs in the te.d., that the write buses are additionally inserted into the RAM block, and the r-t is an additional and wide web-size code for the number-time code sewn sequentially through the first commuting cores of the i-th column t- that, t + 1 th, ..., Е + of Mr. logical cells and through the first commutating cores of the i th logical cells / -fl-ro, i-f2-ro, ..., i (n-fi ) -Toro columns, and the i-ta is an additional bit of the bottom of the write bus of the reverse code of the digit of the number stitched sequentially through the second commutating heart iki 0-howl ,. . . , i-1-, howling, i-th logical cells of the t-th column and through the second co., m., tiruyush, and the cores of the i-th logical cells of the i-1 th, i-2, ... , 0th columns; at the same time, the first address write bus is stitched sequentially through the first commutating cores of the i-th logical

cells of the 0th, 1st, ..., /th of the columns and the second KOiMutating cores (-1th logical cells of the i-th, i + 1th,..., i (ni) -Toro columns, the second write address bus is stitched and successively through the second commutating cores of the t-th logical cells of O-Vogo, 1-iro, ..., i-Toro columns and the first co., mutating cores of the i-1-o logical cells, i- fl-ro, ..., 1 (n - /) - that columns.

This set of logical cells and connections allows, when the factors are in the subjective code, in such a way that after each t-digit of the number A, the i-th bit is followed: Isla B, and successively the world columns of the transposed matrix of partial to obtain the discharges of the product.

Such a need arises in the organization of a parallel computing process on a group of devices.

The scheme of the proposed device

isoorazheya on the drawing.

The device includes a block

control unit, operative memory 2, which includes oneself. a matched node of type 3. a unit of logical cells, each of which contains two commuting cores 4, 5 and one memory core 6 to form a transposed matrix of partial components ; n: Ii, who form the capitals 7 and lines 8; a block of amplifiers reading: 9, blo: To register the number 10 with two-input OR circuits, a block of bit formers of record 12, a selector unit 13, and also a counter M; and a block of output 15. Additional. spikes 16 fronds of the Pramah code of the digit of the number are stitched sequentially through the first co. m., m; t; .e.mmmm. utiruyuschpe core of g-th cells / + 1-st, 1 + 2, ..., i + (n-g) -th of the pillars; Additional bit write busses of the return code of the digit number / 7 are sewn consecutively through the second comm. . ., / -1-howl, Mr-th: th cells of the Mr-th column, and through the second commuting cores of the ith cells; -1-th, / -2- th,. . . , 0th columns; The first address spike of the J8 front was stitched sequentially through the levyz switching cores of r-1TA; x cells of the 0-th l-. ro, ..., 1-tag columns and the second commutating, connectors, I-1-OW cells ( of that, / + 1 st, ..., i + (n-1) columns; the second spike address of the write is 19 lr.shit sequentially through the second commuting heart of the first cells of the first, ..,. , g-stol.btsov and the first to-m mutating hearts, ki / -i-Bi ix what l / -th, i + 1-th, .... i + (n-i) of that column; The address shia was read 20 stitched successively on lines 8, 8 chase, 6 stitch cores, 6 readout spikes 21 — after FIO, columns 7, through memory memory 6.

Control block / in, generates signals, control of the signal. Fulfillment of all power in the device. All operations are filled with the help of a node of logic cells in microprogrammed, m. The prerequisites for the operation, {negsh ulyujeli operation, in particular, for the analysis of the operations, with the p 0 | pt: and the scarlet landscape of the partial objects, is hard 1 the sequence of writing codes of numbers on address buses m / s, and 19 (the bits of the direct reverse of the first number codes are recorded on the address width of 18, 1 of the direct and oraty number of the second number are on the address bus 19).

Drift is consistently ecstatic and both the initial numbers A (ao, ... .. I;, ..., a. ") And B (bo, ... b -, .., bn) take on the dimension that after each / -iToro bit and h.I1SL1a A should be the / th bit of the number B, the forward and reverse codes of the / th bit of the number A, and then the reverse of the codes of the –th time: p The numbers B are written in the corresponding lagging cells so that the other ..y cat of the / th bit is written to the first commutator cores of the column / –th, i-g - your, .., i + (n- / -1; oh cells and first kom., mut; iruyuschuyu: e ser.dechniki / -TH | X cells, / + 2-G-0 ,., i (n - /) - that the column, and the security code of the -th of the bit — the second commuting cores are 0-th, .., -1 -1-th, / -th cells of the column and into the second commutating cores / -th cells / -1th ./ -2nd,., 0-wago columns. Right after that

Pts records: an e | e of an ordinary pair of digits of numbers A – n In the form, the corresponding page of the standard imported matrix of partial products is formed, after reading which by the address bus 20 counter 14 determines the sum of its digits.

At the younger discharge of the counter, the next charge is produced, and the rest of the flog2 ,, -1 (the closest lower integer) digit is the transfer to the higher discharge of the product.

(Before sum.i.ravani.e.m. oc.ed.ed: the column of the matrix of the part of IChl pro, the results of the counterclocker of the counter is shifted by one single bit to the left.

Production bits are called on result register 15, the bit of which is

.and the number of rows of cells to form a transposed matrix of partial. products are determined by the required accuracy of the multiplication results. For example, to get the result of y, multiply with an accuracy of 2

bits,. necessary l-bit result register and 2n build / to the cells.

The consistency of doing the multiplication is as follows:

1) Input to the logical cells of the yes, the numbers A in the forward and inverse “odes.

2) .In the logical cells of the first time; the number of the number B in the forward and reverse codes.

In this case, in the / -th row of trans.01; .and | the | matched matrix of partial products, it is memorized on the first column of the matrix of the partial products.

3) Reads information from the -th line of logical cells L and the register of the number 10.

4) Shifting the contents of the register of the number of vlvOr ia n razdov dov, the census of Mla.diego r. .At the same time

the result register is fixed with the one-th bit of the product, and the tic counter of the quotes to the right and current information of the c / l 1-th row of logical cells.

Well: Kty 3 and 4 are repeated (times), where / can be equal to 0.1, ..., 2 / g, depending on the required accuracy multiplied.

Nssyakolyku in the mode of “augmenting” the time is given for regeneration of cif.ormations, and for losing the item 3 of regeneration of i.ormacin

It is required that the implementation of clauses 4. and 3 may be partially combined in time.

The complexity of the numbers A (ao, ... a, ... a n) and B (b o, ... b, -, ... b) n, p. And their sequential r; exp. The register of the number 10 is a secret image. That after each / th time, the row of the number / 1 is followed by the / -th digit of the number B, it occurs without the participation of log.ic cells.

P | osle.dovatnost vy.polneviya opera.ts.iy at the same time as follows:

1) Acceptance of the jth digit of the number A on the register of the number 10, and of the SDG. IG it to the right for n bits.

2) C. of the 1st digit of the number B by the register of the number 10 and shift it to the right by n bits.

After performing points 1 and 2 at the lowest bit of the detch: Ik 14, a t-tyk bit sum of the sum is formed, and on the next high bit the bit derection in r + 1 bit bit is formed.

3) Transfer the contents of the low-order counter to the output of the result register, shift one counter to the left of the counter and to the right - the result register. In this case, the output register is fixed on the result register, and the head counter to receive} the next bits of the original numbers.

Before you invent

and

A multi-function predictive device that performs arithmetic and logical operations, containing a control unit connected to the memory unit, performed from a memory node and a node of logic cells, each of which has two switching and one memory core about a bit, the transposed matrix of partial products, the first switching core is flashed with a bit of information according to the address, the second is in the opposite direction to the first one, and the memory core is connected to switching circuits of the connection, while the inputs of the RAM block are connected to the block of bitformers, sequentially connected with the register of the number, and the outputs are connected with the corresponding inputs of the block of amplifiers of reading, the outputs of which are connected respectively to one of the inputs of the two-input OR circuits, the second inputs of which are connected to the corresponding registry outputs, the inputs of which are connected to the counter and one of the outputs of the control unit, which is based on the fact that, in order to expand, the functions are possibilities, the block random access memory is further introduced shiiy The discharge recording IRichem that the additional z-bit line code recording direct discharge of sequentially laced through the first

commuting cores of the -th column / -th, / -f 1-howl ,. . . , / + / g-poy logical cells and through the first com: mutated): e cores

/ -TOOL cells / + 1-st, / -r2-th

i + (n- / j-Toro columns, and the second one added the bit of the record of the reverse code of the discharge of the number of the board in series through the second commuting cores 0-th, ..., / -1-th, / -th logical cells / of the second column and through the second commutating non-cores of the 6th logical cells / -1th, / -2th, ..., Oh columns, while the address address write bus is stitched sequentially through the first components of the heart1 ik / -THE logical 1x cells of Oh, 1st, ...

Of the columns .and the second commuting cores of the i-1-τ logical g-cells, i: - 1-st, ... , i + (n - i) -Toro columns, the second address address of the record is stitched by the followers through the second commuting cores of the O-th logic cells. 1st

The first columns and the first commutating cores of the / -1th logical cells of the first, i + 1 (n - /) - columns.