SU377766A1 - DEVICE FOR FORMING OF POSITIONAL - Google Patents

Description

one

The invention relates to the field of computer technology and is intended to convert codes defined in the residual class system (SOC) into positional codes (in particular, into binary code).

A device for generating positional features of a non-positional code is known; it contains input and output registers, a unit for storing constants, adders of constants, a logic circuit for generating signs of a sign and overflowing an input number, a rank adder; however, the known device is a parallel action device.

The proposed device differs from the known one in that it contains a storage unit for shear constants, the inputs of which are connected to the outputs of the input register, and the outputs are connected to the inputs of the shift register, and the analyzer of the sum of high bits, the input of which is connected to the output of the summator of the second bits of the second group of adders of constants , the outputs of the shift register are connected to the corresponding inputs of the input register, the outputs of the registers of inaccurate rank and intermediate result are connected to the inputs of the correction adder, the inputs of the transfer generation unit and from the higher bits are connected to the outputs of the correction adder and the register of the weared result, the outputs of the correction adder and the transfer generation block from the older ones

bits are connected to the inputs of the output register and the circuit for analyzing the contents of the higher bits, which greatly simplifies the device by using the sequential (in groups) principle of processing the fraction bits.

Pa drawing is a diagram of the proposed device.

The device contains an input register / dl

temporarily memorizing the residuals of the input number A on appropriate grounds; a constant storage unit 2 for code conversion and a shift constant storage unit 3 performed on one-way long-term

memory devices 4 for each base, a shift register 5 for temporarily storing residuals, two groups of constant adders (with transfer for one bit) containing 6-W adders, respectively,

adder // rank of number (for summing the carry from the upper bits of adders 6-10), the output of which forms the code of inaccurate rank of the input number, analyzer 12 sum of senior bits generating signals of critical situations when determining rank, sign and overflow the representation range of the input number L; the register 13 is of inaccurate rank, the register M of the intermediate result, the output register 15, the adder 16 of the correction for

summing the contents of the register of inaccurate rank with the contents of the lower bits of the intermediate result register, the generation block 17 of the higher bits, designed to produce a correction of the inexact rank and to get the higher bits of the translated number, the high-order content analysis 18 (translated number) for development of signs of the sign and overflow of the input number, input buses 19, output 20 of the inaccurate rank of the number A, output 21 of the sign of exact rank, output 22 of the position code of the number A, output 23 of the characters and over The input number, output 24 of the correction signal of inaccurate rank.

The device works as follows.

The code for the number A, for which it is necessary to develop positional features, is inputted to input register 1 via input buses 19.

The output signals of input register 1 are fed to the inputs of their memory devices 4. The address for accessing the table of constants is the binary code of the residuals recorded on the input register along the appropriate basis. Binary codes of constants from the outputs of block 2 of storage of constants for code conversion are fed to the inputs of adders 6 and 7, and binary codes from the outputs of block 3 of storage of shear constants are fed to inputs of register 5 for temporarily storing the shifted number A. Shifting register 5 is written to the input register. From the outputs of adders b and 7, the signals of sum and transfer arrive at the inputs of adders 5 and 9.

From the outputs of the adder 9, the signals are input to the adder of the 10 most significant bits to obtain an intermediate sum of the translated number. The transfers generated in the upper bits of adders 6-10 are fed to the summation at the input of the adder / / rank number. From the outputs of the higher bits of the adder 10, the signals arrive at the input of the analyzer 12 of the sum of the higher bits. From output 21 of this analyzer, a signal is output to the control circuit of this device.

The sum signals from the outputs of the adder 10 are fed to the inputs of the output register 15 for temporary storage, and the signals from the outputs of the adder 11 to the input of the register 13 of inaccurate rank. The binary code from the output of AND is the main component in the rank expression of the number A and can be used to perform various non-modular arithmetic operations in the system of residual classes (for example, rounding, division, control).

At output register 15, depending on the pick of the operation of the device, intermediate and final values of the translated number are memorized. The contents of output register 15 are rewritten to intermediate result register 14. From the outputs of registers 13 and 14, the signals are fed to the inputs of the adder 16 and the block 17 for generating transfers from the higher bits. Scheme of the adder 16 can be constructed according to any of the known schemes of adders; the block of generation of hyphenations from the higher bits is constructed from separate half-adders schemes with the organization of the accelerated generation of hyphenations from the higher bits.

From the outputs of the adder 16 and block 17, the amount code goes to the output register 15 and to the inputs of the high-order content analysis / 8 circuit, which generates signals for the end of the sign rank and overflow calculations and thus reduces the influence of the iterative process of forming the positional binary fraction code on

the duration of the calculation of the rank, sign and overflow of the number represented by the nonpositional code.

Subject invention

A device for generating positional features of a non-position code comprising a constant storage unit for converting a code whose inputs are connected to the outputs

the input register, and the outputs with the inputs of two groups of adders of constants, the outputs of the adders of the constants of both groups are connected to the inputs of the adder of the rank of the number, the output of which is connected to the input of the register of inaccurate

rank, the output of the adder of the higher bits of the second group of adders of constants is connected to the input of the output register, shift register, intermediate result register connected to the output of the output register, correction adder, power generation unit of high-order bits in the analysis of the content of older bits, differing from that, in order to simplify the device, it contains a storage unit for shear constants,

the inputs of which are connected to the outputs of the input register, and the outputs - with the inputs of the shift register, and the analyzer of the sum of the higher bits, the input of which is connected to the output of the adder of the higher bits of the second group of adders of constants, the outputs of the shift register are connected to the corresponding inputs of the input register, the outputs of the registers are inaccurate rank and intermediate result are connected to the inputs of the adder correction, the inputs

the transfer generation unit from the leading bits is connected to the outputs of the correction adder and intermediate result register, the outputs of the correction adder and the transfer generation unit from the senior bits are connected to the inputs of the output register and the analysis of the content of the senior bits.