SU375792A1 - FORMAL NEURON - Google Patents

Description

one

The invention relates to the field of radio electronics and can be used in logic devices of automation and computing.

Devices are known for implementing a logic function of equivalence and nonequivalence, which contain current input switches, the OR element on a current switch, and an output current switch with emitter followers at the output.

The purpose of the invention is to increase the reliability and speed of the device.

The goal is achieved by the fact that in the device the input current switches contain a multi-emitter transistor, the collector of which is connected to the collectors of the information transistors of the OR switch and the base of the first transistor of the output current switch, and the collectors of information transistors of the current switches of the switch are connected the current element "OR and to the base of the second transistor of the output current switch, and the emitter followers outputs through diodes, including data in the forward direction are connected to the bases of the corresponding transistors of the output current switch.

FIG. Figure 1 shows the proposed formal neuron (FN) circuit on the current switches, implementing the logical equivalence function, ..., XnVXiX, ..., Xn on the direct output and the non-equivalence function f (XiyX2V, ..., VXn) (XiVX. V, ..., VY ,,) on the inverse output.

As can be seen from FIG. 1, the FN contains the input current switches formed by the information transistors / i, 2, ..., In and the reference multi-emitter transistor / "- c, the element" OR on the current switch consisting of the information transistors / "- i-a. / 71 + 3, .... hn + z. The circuit also contains an output current switch on transistors 2 and 3, from whose collectors direct and inverse output signals (F and P) are removed through emitter followers 4 and 5. The current switches formed by the transistors li, h, - .., / n + ь correspond to the positive inputs of the threshold element FN (Fig. 2), and the switch current is formed by the transistors. "- 1-2, / n + s, .. ., / 2П + 2, corresponds to the negative input of the threshold element FN.

FIG. Figure 2 shows a fuctional image of an FN that implements an equivalence (nonequivalence) function. The transistors n + 2, n + 3, ..., / 2i +, 1 in FIG. 1 correspond to the inputs of the element “OR” in FIG. 2

The device works as follows. In the absence of input signals, i.e., when x2, ..., the transistors / ij / 2, ..., 1.1 are locked, and the transistor In + i is open through all the output transitions; In + z, 1п + з, -.-, 1гп + transistors are locked, and 1п + transistor. open to all emitter transitions; the transistors / n + 2, n + z, ..., Izn + i are locked, and the transistor / au + g is open. Since, (where R, Rz are the resistances of n resistors 5 and 7), the currents flow through the resistors 8 w. 9 are the same. Since, then. Therefore, if h, is the resistance of the resistors 5 and I, the transistor 2 is open and the transistor 3 is closed. As a result, at the direct output (F) of the element we have a high potential level (logical "1), and at the inverse output (F) we have a low potential level. If the signals are present at all inputs of the circuit, i.e., ..., An l, then the transistors L, 2, ..., In are open, and the transistor / n + i is closed for all emitters, the transistors In + z, - / п+з,.-., / 2П + 1 are open, and / 2И4-2 is closed. Again, the currents flowing through the resistors 8 and 9 are equal, and therefore the transistor 3 is closed, and 2 is open, and at the direct output of the circuit we have a high potential. In all other cases of combinations of input signals, transistor 5 is open, and 2 is closed, i.e., at the direct output of the circuit, we have a low potential level (logical 0). Diodes 10 and 11 serve to prevent saturation (direct displacement of the collector junction) of transistors 2 and. In the proposed scheme, the saturation of the transistors of the input switches is prevented by means of diodes 12 and 13 connected between the collectors of these transistors and the circuit outputs. Consider an example. Let, Hd, Xs, ..., Xn 0. Then a current flowing through the resistor 8 is equal to (2n -}) / i (/ i-current going through pe5 10 15 20 25 30 35 40 resistor 6). for large n, this current is sufficiently large and the potential at point b is greatly reduced. As a result, the collector junctions of the transistors / n + i, 1п + 2, - .., lzn + can be displaced in the forward direction, which leads to saturation of these transistors, an increase in their turn-off time, and consequently a decrease in the speed of circuit B in general. Diodes 2 and 13 allow the potentials at the collectors of the input transistors to be fixed at the level, - - dB (where f / B is the high potential, Uf is the voltage drop across the diode), thereby preventing the saturation of these transistors. Subject of the invention A formal neuron for implementing a logic function of equivalence and nonequivalence, which contains input current switches, the OR element on current switches and an output current non-switch with emitter followers output, characterized in that, in order to improve reliability and speed of operation, in it, the current input switches contain a reference multi-emitter transistor, the collector of which is connected to the collectors of information transistors of the current element “OR” and with the base of the first transis of the output current switch, and the collectors of information transistors of the input current switches are connected to the collector of the reference transistor of the OR switch and to the base of the second transistor of the output switch, and the emitter repeaters are connected to the bases of the corresponding output transistors current switch

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