SU374745A1 - UNIVERSAL LOGICAL ELEMENT - Google Patents

Description

one

This invention relates to the field of computing.

A universal logic element (ULE) is known, which contains diodes, two input windings on each of four cores with a rectangular hysteresis net, compensating winding, read winding and output windings.

The principle of operation of this element is based on switching clock pulses to the output price corresponding to a non-reversible core. However, clock sources have increased power. In addition, false signals are possible, and all the windings cannot in principle be made single-turn.

The purpose of the invention is to reduce power consumption and increase the reliability of the device in operation. This is achieved by the fact that one input windings of all the cores are connected in series, with the windings of the first and second cores included opposite the windings of the third and fourth cores. The other input windings of all the cores are also connected in series, with each one being connected in opposite with respect to the previous one. The same ends of the input windings are combined into a common bus, and the same ends of the output windings are connected to the input of the amplifier.

The drawing shows a schematic diagram of the proposed element.

The element allows all sixteen logical functions of two variables to be implemented. It has input terminals 1 vi 2. A current pulse is connected to each of them only if there is a logical unit at this input. The clock pulses shifted relative to each other are connected to the terminals 3 and 4.

To implement any of the sixteen logic functions, it is necessary to connect terminals 5-8 in a certain combination with the input 9 of the pulse amplifier 10, and its output // with one of the inputs of the next element.

The current impulses to the input terminals of the element are simultaneously nodded with the clock pulses arriving at terminal 3. With any combination of binary information, one ferrite core at the input terminals of the element is internally alternated. Impulse induced in its output winding does not pass to the input of a pulse amplifier. Upon subsequent reading by a clock pulse arriving at terminal 4, this ferrite core, returning to its original state, and in the output winding has a pulse of opposite polarity passing to the output of the pulse amplifier.

When implementing a disjunction on terminal 9

It is necessary to send signals from terminals 5, 6 and 7. The input of the pulse amplifier should be connected only to terminal 5, etc. The negation of each function is realized by inverting the connection of terminals 5-8 to input 9.

Any logical operation is performed in one clock cycle, and in the next clock cycle the result can be written to the second element.

Subject invention

A universal logic element, made on cores with a rectangular hysteresis loop with two input windings on each core, output windings in series with which the diodes are connected, and clock buses, and containing an amplifier, characterized in that in order to reduce power consumption

and increasing the reliability of operation, the input windings of all the cores are connected in series, forming two circuits, and in one circuit the windings of the first and second cores are connected oppositely to the windings

the third and fourth cores, in the other circuit, each subsequent winding is connected oppositely to the previous one, the outputs of both circuits are combined, with one of the clock tires passing through the first and fourth

cores, and the common bus of the output windings is connected to the input of the amplifier.

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