SU373894A1 - DEVICE FOR SERIAL DECODING - Google Patents

Description

I

The invention relates to the field of transmission of digital messages over communication channels, in particular, to noise-interference coding devices.

A device for sequential decoding of convolutional codes is known, comprising a buffer store, an encoding register, a parity check block, a counter, an adder, a random-access memory block, and an encoding register.

However, in the known device, the input of the RAM block is connected to the output of the buffer accumulator, which makes it necessary to enter into the circuit a register of decoded characters, which during the reverse run recovers and subtracts all partial differences added during the forward run during the return accumulator.

The introduction of the register of decoded characters increases the cost of the device and increases its complexity.

In order to simplify in the proposed device, the input of the RAM block is connected to the output of the parity check circuit, as a result of which the register of decoded characters is excluded from the device circuit.

The drawing shows a block diagram of the proposed device for sequential decoding of convolutional codes.

The proposed device contains a buffer drive /, a coding register 2, a parity check block 3, a counter 4, an adder 5j a RAM block 6, the input of which is connected to a parity check block.

Coming from a communication channel, a binary sequence of symbols is recorded in groups of data in buffer storage 1, from where it is read and fed to parity checker 3, with one data group being read from each buffer of operation of the device. Each data group contains one information symbol and corresponding verification symbols. At the same time, a hypothetical character, presumably corresponding to the transmitted one, is written to the first (left) bit of the coding register 2.

informational. The value of the symbol is chosen in such a way that the obtained hypothetical data group most closely matches the channel group read from the buffer accumulator (due to possible distortions in the communication channel, a complete match of the data groups may not occur).

A hypothetical group of data is formed by modulo-2 summation of legally selected convolutional code of characters written in the coding register. The parity block 5 adds and compares modulo 2 channel and hypothetical data groups.

The frequency difference obtained from the output of the parity check block is recorded in memory block 5 and fed to counter 4, which counts the number of mismatched positions of the hypothetical and channel data groups, i.e., calculates the weight of the partial difference. Then this number is added to the content of adder 5, which records the total discrepancy between the hypothetical and channel sequences created by all the previous data groups.

With each cycle of operation of the device, the content of the coding register is shifted by one bit to the right. The characters reaching the right end of the register are read correctly and are returned to the receiver.

If the discrepancy between the hypothetical and, G-channel sequences is fixed; . With the adaptive adder 5, the preset threshold T, then the hypothetical Prs11 dB & does not correspond to the 25, 1-and-sweat1; Ceska sequence changes. For this, the weight of the most recent partial difference is read from the contents of the adder, which is read from the RAM block 6. The character in the left 30 bit of the coding register is inverted, and the weight of the corresponding partial difference is added to the contents of the adder, the cell contents of block 6 are updated .35

If, an attempt is made to advance to the right, a new group of data is selected from the buffer accumulator. Otherwise, the hypothetical sequence is shortened and previous symbols are changed. For this, the coding register is shifted left by one bit, and the character appearing in the left bit is inverted. The shortening of the sequence continues until the condition is met.

When shortening a hypothetical sequence, the weight of the partial differences related to the cut-off groups is subtracted from the contents of the adder, and then the frequency differences are selected from block 6, and the restored channel data groups are written in their place.

The restoration of the channel data group is performed by the parity check block 3, to which the hypothetical data group and the partial difference from the RAM block are supplied. Restoring channel groups eliminates the effect of decoded symbols on them.

Subject invention

A device for sequential decoding of convolutional codes, comprising a buffer drive, an encoding register, a counter with an adder, a memory block connected by an output to a parity check block, characterized in that, for the sake of simplicity, the input of the RAM block is connected to the output of the block parity checks.

Information / and from the channel

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