SU309363A1 - CENTRAL PROCESSOR OF THE MULTIPROGRAM MULTIPROCESSOR COMPUTING SYSTEM - Google Patents

Description

The invention relates to computing and, in particular, to the structure of a central processor multiprogram multiprocessor computing system, which includes a set of specialized processing devices.

Known central processors multiprogram multiprocessor computing system containing the processor commands; a fixed point execution processor including a set of general registers; a floating point execution processor including a set of floating point arithmetic registers; a main memory management device and a main extended memory management device. Moreover, in the execution processors, buffer operand registers and operation code stores connected to the output of the instruction processor instruction register register, floating-point arithmetic registers, operand buffers, and the floating-point arithmetic operation code store are connected to the processor execution units that General registers, operand buffers, and the fixed-point arithmetic operation code store are connected to the execution unit of the processor to perform fixed-point operations. The floating-point arithmetic registers and the execution unit of the fixed-execution processor are connected to the information buffer of the main memory management device. The disadvantage of the known processor is the complexity of the structure of individual specialized devices. By certain changes in the structure of a known processor, greater potential performance can be achieved.

The proposed central processor differs from the known one in that it contains in the processor of instructions a switching circuit for transmitting commands for decoding directly from the registers of the instruction buffer; a quick preliminary check circuit and an exact check pattern of the addresses of the memory cells when preparing the storage operation with the addresses of the instructions in the instruction buffer; a scheme for recording commands directly from the information buffer of the memory management device recording device when the address of the memory location in which the recording is made with the address of a command stored in the instruction buffer of the command processor simultaneously coincides with recording into the memory location; separate buses transfer read and write requests from the processor

transitions, speed up the operation of the computer, and retain the contents of the instruction buffer registers if there is no transition.

The first 16 bits of the decoded instruction and the next 32 bits from the instruction buffer registers are sent to the decoding via the switching circuit 17 using the decoder 18.

The length of the command is added to the address of the decoded command recorded in register 4 on the adder 19, and the result (address of the next command) is stored in bits 40-63 of the register 20 of the program state word.

In the transition to decoding the next command, the address from register 20 is placed into register 4. Using the decoder 18, the command buffer registers the first 16 bits of this command and the next 32 bits, and so on, for decoding.

Commands are decoded in a command decoding unit 21 and placed into a command register 22, from which, under the control of the collision analyzing unit 23, are sent to a fixed-point processor 24 or a floating-point processor 25 to operation code stores 26 and 27. The decoded transition and state switching commands are sent by block 21 to block 28 for performing transition commands and state switching, where they are performed with the assistance of block 23 of conflict analysis.

In block 29 of modifying the address of the instruction processor, the address of the operand and a request to the memory management device under the control of the collision analysis block 23 are generated. A request to fetch the operand is sent through the switch 5 and the register 7 of the read request under the control of the circuit 6. The write request formed in the address modification block 29 controlled by the conflict analysis block 23 is sent to the write address buffer 30 in the main RAM memory by a separate bus 31.

If a write request is made, the quick check circuit 32 determines in advance whether the memory operation affects the contents of the command buffer 10.

If such an influence is determined, the sampling of commands and decoding are blocked, an exact check circuit 33 is included which compares the address of the memory cell into which the memory will be made with addresses in the registers M and 3.

Register 3 marks the address of the first double word of commands placed in the command buffer. When, as a result of increasing the address in register 2, the three lower order bits of the double word address in this register coincide with the three lower bits of the double word address in register 3 when the request is sent to the main random access memory control unit on the double word sample

commands, the unit is added not only to the address in register 2, but also to the address in register 3. Adding one to the address in register 3 is done on adder 34, and the result is stored in intermediate register 35. When the request is completed, the output of register 35 is connected to the input of register 3. The coincidence of the three least significant bits of the address in registers 2 and 5 indicates that the buffer 10 kompapd is full and on subsequent samples of command double words the command double words are replaced that are in this buffer, starting with the first one.

A lock is released if the result of an exact check indicates that storing the ne does not affect the contents of the command buffer. If the address of the memory cell in which the zanomapia will be produced matches the address of a command in the command buffer,

This lock is not released until this command is replaced with a new one. As soon as the information for storing enters the recording information buffer 36, the lock is released. This replacement is made

diagram 37.

A complete request to the main operating memory management device, in addition to the address of the memory cell, also contains a memory protection key, a write flag or a read flag,

address of the destination register and the marker.

The four-bit memory protection key serves to protect certain areas of the memory from erroneous sending of information during the execution of a program.

For protection purposes, the operational memory is divided into blocks of 256 double words (2048 bytes). A memory key is associated with each unit. Fifth bit is used to protect against sampling.

When accessing the memory in the main RAM control device 9, the four-bit security key is copied with the four bits of the memory key. Recording and reading are allowed if

this is a match or, in all bits of the bullet protection key. If the security key is not a bullet and does not match the four bits of the memory key, the entry is not allowed. A thread is allowed if it is fifth grade. the memory key is zero and not if the unit.

The security key is stored in register 20 of the program status word. Memory keys are stored in memory block 38.

keys and enter the main memory management device via the slit 39. The memory keys are set by the command "Install the memory key and checked by the command" Read the memory key by the block 28

executing transition and state switching commands.

Since the memory operates with double-length words, and the commands operate with length information (byte, half-word, word,

High performance is also achieved due to the reduction of the time of access to the memory and the time of execution of operations, a high degree of combination of operations, parallel execution of programs and the use of high-performance algorithms.

In order to reduce the time for accessing Y, the main operative memory is divided into four blocks with independent control in such a way that neighboring programs and information on neighboring addresses are stored in different blocks and are independently selected from them. With such an organization of memory, the average access time to memory is reduced in the general case in proportion to the degree of separation (partitioning). However, in the real world of problem solving, accessing individual memory blocks is unevenly distributed in time. To smooth out such an uneven distribution of calls to the individual memory blocks and match the sampling time and the execution time of the operations, buffer memories are introduced into the processor.

Various kind of other buffer devices of the processor are used to organize the combination of operations. With the help of buffers, a queue is built, unevenness is smoothed when performing operations at different levels, and the intermediate results are memorized. Such a small memory has a speed of the same order as the speed of the logic circuits.

The buffer memory in the central processor allows to accumulate command and numerical information during the operation of arithmetic units, as well as to start the execution of the next operation, without waiting for the previous one. The structural scheme of the central processor implements the principle of maximum combination of simultaneous operation of each unit with the work of the others. At the same time, the optimal consistency of the work of individual blocks is ensured by a system of communications between them.

Due to the coordinated parallel operation of individual blocks, the performance of the proposed central processor does not directly depend on the time of each individual operation.

Efficient use of the high performance of the proposed CPU when working with external devices and I / O devices is achieved by organizing multiprogram work. When two or more programs are executed simultaneously, their protection against mutual influence is provided. Management of multiprogram work is carried out by a special control program.

A series of elements of the proposed CPU provides automatic memory allocation, protection of the memory areas occupied by a task from possible

alarms to them when solving other tasks; automatic switching from one task to another.

It also provides for the joint operation of several processors.

An interrupt system is used to programmatically control external exchanges and automatically switch from one task to another.

FIG. 1 given the structural scheme of the proposed CPU; in fig. 2- a block diagram of the conflict analysis block, coordinating the work of individual buffer stages of storing information, is developed. Commands from the memory into the processor 1 of the commands are selected by 64-bit (double) words. The address of the first double word of commands is placed in registers 2 and 3 ..., the address of the first command is in register 4. From the output of register 2 through switch 5 under the control of the sampling control circuit 6, the address is sent to register 7 of the read request and further on read request to main memory management device 9. The three low-order bits of the command double word address indicate the register number of the 10 command buffer, in which the double word of the command selected from the memory should be placed. At the accumulator I, a unit is added to the address of the first double word of commands and the result (address of the second double word of commands) is stored in intermediate register 12, and the address of the first double word of commands is stored in intermediate register 13. When the request for the first double word of the commands is transmitted, the output register 12 is connected to the input of register 2, the output of register 13 is connected to the input of register 14. In register 12, this is the address of the second double word command. A request is sent to select the second double word of commands, after which register 2 sets the address of the third double word of commands, etc. until one of three conditions occurs: a) requests for five double words of commands are transmitted (when transmitting requests for four words are additionally sent a request for one more command word, if this does not delay the transmission of the request for the operand; b) a conditional mode is established as a result of processing the "Conditional Jump" command;

c) non-uniformity is detected, i.e., the sampling process is interrupted as a result of transition, interruption or storage operations. The command double words selected from the memory are stored in the buffer registers of the 10 commands or in the additional buffers 15 and 16.

Additional buffers are used when processing transition commands. They record the first two double words of the new sequence commands, the processing of which begins if the transition is successful. These buffers provide a start in case of a successful buffer register. This node consists of a register 76, which consists of six independently controlled triggers in accordance with the number of buffer registers of the processor for performing floating-point operations, the generation scheme of the free buffer register 77 and the signaling circuit 78 of the presence of floating-free operations in the processor. buffer register.

When processing a command belonging to the class of floating point commands that use the information stored in the memory, the collision analyzer checks the processor for performing operations with the floating point of a free buffer register, and the signal on the 79 79th panel produces a three-bit free code. the buffer register, which comes along the command line 80 to the command generation circuit in the decoding unit 2 / commands and the request generation circuit in the address modification block 29 and stores the occupation of the selected free buffer Registers at a corresponding flip-flop (signal busy on schine 81 enters processing for the next instruction). When the processor 25 performing the floating-point operations uses the contents of one or another buffer register, it signals this block 23 of conflict analysis on bus 82, including the corresponding register trigger 76. The status of the trigger on bus 55 is fed to the analysis in register 77 and circuit 78. The operation of the node for analyzing the state of the buffer registers of the floating-point execution processor controls the signal via the strip 84 from the control signal generation circuit S5.

The state of analysis of the state of the buffer registers of the processor performing fixed-point operations is intended to signal the presence of free buffer registers in this processor and to generate a code for the free buffer register. This node consists of register 86, which is the name of independently controlling triggers according to the number of buffer registers in the processor 24; circuit 87 generating code free buffer register; analysis 88 of the availability of a free buffer register in the processor 24 of the three-bit counter 89 for counting the number of occupied buffer registers and the circuit 90 analyzing the number of unused buffer registers.

When processing a command belonging to the class of commands of arithmetic with fixed occupation, using information stored in the memory, the conflict analysis block 23 checks for the presence of a free buffer register in the processor 24 (signal 97) and, if so, the circuit 55 generating control signals on the basis of the processed command of the collision analyzing unit 23 outputs to the node analyzing the state of the buffer registers of this processor a control 12

the transmitting signal on the bus 92, arriving at the circuits 87, 88 and the counter 89.

On this signal, the circuit 87 on the tongue 93 issues the three-bit code of the free buffer register of the processor 24 to the instruction decoding unit 21 on the instruction generation circuit and to the address modification unit 29 on the query generation circuit; circuit 88 sends to the corresponding trigger register 86 a busy signal of the selected buffer register via bar 94; The counter 89 remembers the fact of the next selection of the buffer register of the processor 24.

When processor 24 executes the next command using the contents of the buffer register, it signals this conflict analysis block 23 for clearing the buffer register 95 by turning off the corresponding register 86 trigger and subtracting "1 from the contents of counter 89. The state of the register 86 trigger on bus 96 arrives at analysis circuits 87 and 88 — to generate a new code of the free buffer register, and information from counter 89 via bus 97 arrives at scheme 90 for analyzing the number of free buffer registers, since I meet The PC commands are fixed-point arithmetic, which requires the processor to have two free buffer registers. The signal along the busch 98 from the circuit 90 signals the presence in the processor 24 of more than one free buffer register.

The node for analyzing the state of the buffer registers of the memory management device is intended to signal the presence of a free buffer register in the device and generate a free buffer register code. It consists of a register 99, which is three independently controlled flip-flops in accordance with the number of buffer registers in the main memory management device 9, a circuit for generating a free buffer register code 100; The analysis of the availability of a free buffer register in the device 9. When processing the memory commands, the collision analysis unit checks the fact that the device 9 has a free buffer register (the signal from the slit 102} and, if any, the control signal generation circuit 55, on the basis of the processed command, issues the node of the analysis of the state of the buffer registers of the device 9 control signal on the bar 103, arriving at the circuits 100 and 101.

According to this signal, the circuit 100 on the tongue 104 outputs the two-digit code of the free buffer register of the device 9 to the command register 22 and to the block 29 to the query generation circuit; The circuit 101 outputs to the corresponding trigger of the register 99 a busy signal of the selected buffer register along the bus 105. When the device 9 records the information from the buffer register into the cell, it signals the block 23 for analyzing conflicts on the bus

Neither the required information nor the double word requires special signs.

The location of the required information is indicated in the request using an eight-bit marker (according to the number of bytes in a double word).

Regardless of the length of information that needs to be written to the memory, its beginning in the registers of the information buffer 36 of the record always coincides with the high-order bit.

From the buffer 36, information is transferred to the shift circuit 40, which supplies information to the bus 41 to the main RAM memory control units and the bus 42 to the extended RAM memory management device in accordance with the token of the corresponding write request.

The information selected from the memory comes over the bus 43 in accordance with the marker in the corresponding read request to the input register 44. Simultaneously with the information from the memory, the address of the destination register arrives on the bus 5, which is placed to register 46, and the marker on bus 47 to register 48. By shifting circuit 49, the information is shifted so that its beginning always coincides with the high register of the receiver register, and is fed via bus 50 to the register defined by the address of the receiver register under control of g cipher 51 addresses of the register-receiver.

In addition, from the register 44, information is fed to the transmission control circuit 52.

Commands that operate on variable-length information can be performed both in software and hardware. When using the program method, such commands cause the program to be interrupted, according to which a routine for executing such commands is called from the memory.

To execute commands operating with variable length information, the hardware method provides for the possibility of connecting a specialized unit.

In this case, the program is not interrupted, and the operation code from the command decoding unit 21 is supplied to the specialized unit via the bus 53.

Bus 54 sends a signal to the command decryption unit that a dedicated unit is connected, through which the interrupt is blocked when decrypting commands operating with variable length information and allowing the transfer of the operation code of these commands.

Interrupt block 55 processes program interruptions when signals external to the system appear, as well as signals coming from input / output devices or appearing in the central processor itself.

Communication with other central processors of the system is effected via buses 56 and 57 through an input / output unit 58.

The control I / O channels are connected via buses 59 and 60 through the same block 58, which participates in the processing of I / O commands and direct control.

The central processor is connected to the main extended memory blocks via the main RAM control unit 61 and the main extended memory control unit 62 via the address bus 63 and the information bus 64.

The main extended memory control unit 62 is associated with the input and output channels of the bus 65.

The bus 66 from the main memory management unit 61 is used to transmit the address when accessing the blocks of the main extended random access memory.

All floating point commands are executed in the processor 25 for performing floating operations, in which, in addition to the operation codes store 27, there is an addition block 67, in which operations of addition (subtraction) are performed with normalization of the result

and without normalization and comparison; a multiply and divide unit 6S in which multiply and divide operations are performed; floating-point arithmetic registers 69 for temporarily storing the results of floating-point operations; a buffer 70 of operands in floating point arithmetic designed to buffer operands coming from RAM; descrambler 71 opcode.

A fixed-point processor 24 is designed to perform fixed-point arithmetic and logical operations. The processor 24, except for the store 26 coke operations.

contains an execution unit 72 performing arithmetic and logical operations; a buffer of 75 operands of fixed-point arithmetic, intended for buffering operands coming from operational

memory; decoder 74 opcode; general purpose registers 75 for temporarily storing the results of fixed-point operations. General purpose registers are directly connected

with a processor / instruction that can access general registers, write and read information from these registers.

In some cases, a fixed-point processor 24 may take operands from a buffer 70 of floating-point arithmetic operands that is associated with a buffer 73 of fixed-arithmetic operands.

The node of analysis of the state of the buffer registers of the processor performing floating point operations is intended to signal the presence in the processor of performing floating point operations free buffers121. Along with the functions described above, the circuit 121 stores the numbers of three general registers, the contents of which will be used when executing instructions of the processor 24. Information on these registers is received on buses 135 and 124 from block 21 and is four-digit codes containing the numbers of the general purpose registers 75. The circuit 121 signals the bus 136 to memorize the numbers of the general purpose registers, the contents of which will be used when executing the commands of the processor 24. The memory is performed on the counters 133, the numbers of which correspond to the numbers of the general purpose registers.

When the processor 24 executes a command using the contents of general register 75, this processor issues to the conflict analysis block 23 to the bus counter 133 via the / 57 signal, by which this counter subtracts "1 in the corresponding counter and the counter is reset to zero, meaning That this general register is free from its use in commands with a fixed comma.

When processing processor commands, the result of which is a change in the general register 75, it is necessary to ensure that the information is entered only in the register which is free from use in processor commands 24. This function is performed by the general register occupancy analysis 134 for processor commands. Circuit 134 receives information about general registers, the contents of which will be changed as a result of the execution of instructions by processor 24 (bus 129); information about general registers whose contents are used when executing instructions by processor 24 (bus 138); information about the general purpose register, the contents of which will change as a result of the execution of a command by the processor 24 (bus 139) and the indication of processor commands that change the contents of the general purpose registers (bus 140).

The result of the analysis from the circuit, / 54 as a signal on the bus 141 enters block 29 and either enables or prohibits the recording of information in register 75 as a result of execution of a command by the processor /.

The command flow control node is intended to detect conflicts that may arise when a parallel method of processing several commands is received at different levels. It consists of a register 142, which is three independently controlled flip-flops designed to fix features that can interrupt the continuous processing flow caused by the effect of program instructions on each other; inter-command lock analysis circuits 143, register 144, which are three independently controlled registers for capturing features that can interrupt a continuous stream of command processing due to conditions other than the commands being processed; and interlock analysis circuits 145, independent of the commands being processed.

When processing memory commands, a situation may arise when the result of executing the next command affects the command

following her. In this case, it is necessary to stop decoding the next command until the memory command is completed. When processing the memorization command, the conflict analysis block

this command on one of the register triggers

142 (signal along the splint 146 from block 21). The quick check circuit 32 provides a signal to the register 142 via the bus 147, which signals the possibility of such an effect. The circuit 143 in this case generates a signal on the bus 148, which enters block 21 and blocks the supply of commands for decryption and the circuit for blocking the generation of control signals.

After the final determination of the effect of the memory command on the commands following it, the circuit 33 generates a signal on the bus 149, which either confirms the effect of the signal on the bus 147 or cancels it.

The information from register 142 is transmitted to analysis circuit 143 via bus 150. Another case of the occurrence of inter-command locks occurs during the processing of transition commands. In this case, it is necessary to stop the execution of the next commands of the program until the decision on the transition is made. For this circuit

143 receives from block 21 the signal of the sign of the transition command on the bus 151.

When processing program commands, situations arise when it is necessary to stop the execution of commands under the influence of conditions that require a transition to the processing of other programs or subroutines. These conditions include the arrival of signals from the unit

55 interrupts (signal on the spindle 152), from the timer (signal on the bus 153) or operator intervention (signal on the spike 154). In any of these cases, the circuit 145 generates a blocking signal on the bus 148 based on the analysis of the contents of the register 144 arriving at the circuit 145 via the bus / 55. On the other hand, the circuit 145 itself generates an interrupt signal, which is fed via bus 156 to interrupt unit 55. If this block receives a signal

for execution, he reports this to the conflict analysis block 23 by sending a signal via bus 152, and that, in turn, interrupts the processing of the main command stream.

The reason for the generation of the interrupt signal on bus 156 is the circuit 145: the absence of equipment in the system to execute certain commands (bus signal / 57), since in this case they are

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106 about releasing the buffer register by dropping the corresponding trigger register 99. Information about the state of the trigger register 99 via bus 107 goes to analysis circuits 100 and 101 to generate a new code of the free buffer register of the device 9.

The node of the analysis of the state of stores of operation codes of processors with fixed and floating point is intended to signal the ability of processors to accept instructions for execution, i.e., that processor instruction stores have free registers for receiving instructions. It consists of a four-bit counter 108, which records the number of commands transmitted to the processor 25; a three-bit counter 109, which records the number of instructions received by processor 24, and the circuitry 110 of analyzing the ability of processors to accept the next sequential instruction to the store.

When processing a floating point command, the collision analysis block checks the ability of processor 2.5 to receive a command to execute on a signal via bus 111 from circuit 110. If the answer is positive, circuit 85 of collision analyzer 23 outputs a signal to bus 108 via bus 112, which the counter remembers the fact of sending the command to the processor 25. Upon completion of the execution of the next command, the processor 25 issues a signal in block 23 to the conflict analysis unit on the counter 113 to the counter 108, which signals the release of one of the eight store registers of the operand codes walkie-talkies. Similarly, when processing a command with a fixed comma, the collision analysis block checks the ability of the processor 24 to receive a command to execute on a signal from SCHNE.114 of the circuit 110 and, if the answer is positive, the circuit 85 of the collision analyzer 23 outputs the signal on bus 115 to counter 109 This counter remembers the fact that a command was sent to the processor 24. Upon completion of the execution of the next command, the processor 24 issues a signal on the bus 116 to the counter analysis block at the counter 109, which signals the release of one of the six registers. opcode. The contents of counters 108 and 109 over buses 117 and 118 enter circuit 110 for the following analysis.

The common register occupancy analysis node for address modification is intended to control the flow of information into the modifier adder. The node consists of 16 three-bit counters 119 in accordance with the number of general registers that are in the B processor 24, the general register occupancy analysis circuit 120, and the general register registers control counter circuit 121. When processing a command belonging to the command class of arithmetic with a fixed comma, as a result of the execution of which the contents of the general-purpose register will change, the circuit 85 of the conflict analysis block generates a signal

on the bus 122 arriving at the circuit 121.

Circuit 121 remembers the fact that the general register contents were changed by issuing a signal on bus 123 to a counter whose number corresponds to the number of that general register whose contents will be changed as a result of the execution of a command from processor 24. To generate signals

meter control 119, the circuit 121 receives from the output stage of block 21 via bus 124 the four-digit code of the general register number 75, the contents of which will be changed, and the signal 125 is a sign of the commands that change

the contents of general registers.

When the processor 24 executes the command, as a result of which the contents of the general register change, the processor signals this to the conflict analysis block 23, issuing a signal on the bus 126 to a counter with a number corresponding to the number of the general register whose contents have changed. With this signal, "1 is subtracted from the contents of the corresponding counter,

and the counter goes to the zero state. This means that this general register is free. When processing commands that require modification of the address with the contents of the general registers, before sending the contents of the general registers to block 29, it is necessary to make sure that the general registers whose contents will be used are free.

This function is performed by common register occupancy analysis circuit 120 to modify

addresses. On buses 127 and 128 from block 21, circuit 120 receives the numbers of general purpose registers, the contents of which must be transferred to block 29, and on bus 129, information about the state of general registers in

this moment. As a result of the analysis, the circuit 120 generates a signal on the bus 130, which is fed to the circuit 85 of the conflict analysis block and contains information allowing or prohibiting the transfer of the contents of the general purpose registers to the address modification block 29. When allowing use of the contents of the general purpose registers to modify the address, the circuit 85 generates control signals arriving

in blocks 21 and 29 for tires 131 and 132.

The general register occupancy analysis node for the processor / command is intended to control the entry of information into the general registers as a result of the execution of instructions by this processor modifying the contents of the general registers. It consists of 16 three-bit counters 133 according to the number of general-purpose registers; schema 134 analysis of the scheme

121 management counters occupancy. When processing a command belonging to the command class of fixed-point arithmetic, the circuit 85 of the conflict analysis block 23 generates, as described above, a signal of half word, word and double word when transmitting information from the recording information buffer to the memory blocks and to the boundary double word when transferring information from memory blocks to the operand buffer of floating point arithmetic and the operand buffer of fixed arithmetic, it contains the exhibition marker transmission buses from the address modification circuit to the address buffer in the record, from the register of the request for reading a cue to the main RAM memory control unit and from the main RAM memory control unit to the command processor, with the memory and the command processor being switched on an additional shift register with the transfer control circuit, and between the information write buffer and memory shift pattern. 4. The central processor of the multiprogrammed multiprocessor computing system-20 of the system in accordance with claim 1, characterized in that, in order to reduce the equipment, in it the conflict analysis block contains the nodes of the analysis of the state of the buffer registers of the processors performing operations with fixed and floating comma and main memory management devices, including input registers, schemes for generating free buffer registers, and schemes for analyzing the presence of free buffer registers associated with control outputs with input Registers; nodes of analysis of the status of stores of operation codes of processors with fixed and floating point, containing counters of the number of commands in execution units and a scheme for analyzing the presence of free cells in stores related to the outputs of the node counters, a node of analysis of general purpose registers for the modification block addresses, including a set of counters of the number of commands for changing the contents of any general register, a signal circuit for releasing general registers connected to the modifier, and counter control circuit, general register occupancy analysis node for processor commands containing a set of counters with a control circuit and a general purpose register release signaling circuit when the processor commands are executed, a continuous command interrupt node that includes analysis of locks that are not dependent on the processed commands, and the analysis of locks caused by the influence of commands on each other, and buffer registers for storing the conditions causing the locks connected to the corresponding yuschim inputs of the first and second circuit node.

65 S1 BJ 66

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commands for incorrect execution, for example, violation of the location of information in the memory in accordance with boundary conditions (signal via bus 158 from block 29) or violation of specific conditions imposed on the information contained in the command components (signal via bus 159 from circuit 85 ). In the last two cases, you need to go to the program to find the cause of the violation of specifications.

The control signal generation circuit 85 is designed to control the operation of all of the listed nodes of the conflict analysis block 23. The circuit receives information about the state of all nodes of block 23 and, on the basis of this, outputs a set of control signals. In addition to the signals listed in the description of the nodes, the circuit 85 receives information from block 29 on the status of the address modifier E (signal via bus 160) and from block 21 the sign of the command being processed via bar 161; and the format of the command being processed via the bus 162. For each command currently being processed, the circuit 85 checks that all the conditions under which the command can be executed is executed, and only in this case gives a set of control signals to those or other nodes. If any condition is not met, circuit 85 does not issue control signals until these conditions are met. Thus, circuit 85 may suspend processing of a stream of commands for the duration of the required conditions.

Subject invention

1. The central processor of a multiprogram multiprocessor computing system containing the instruction processor; a fixed point execution processor including a set of general registers; a floating-point processor, comprising a set of floating-point arithmetic registers, a main memory management device and a main extended memory management device, the operand processors and operation code stores connected to the processor command register output in the execution processors commands, registers of floating arithmetic; operand buffers and the floating point arithmetic operation code store are connected to the execution units of the processor to perform floating point operations; general purpose registers, operand buffers, and the fixed-point arithmetic operation code store are connected to the executive unit of the processor performing fixed-point operations; The registers of arithmetic with a link, its comma, and the executive unit of the processor performing fixed-point operations are connected to the information

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the write buffer of the main control device operatively; memory, characterized in that, in order to simplify the structure, reduce equipment and improve performance, it contains in the command processor a switching circuit for transmitting commands for decoding directly from the command buffer registers, a fast preliminary check circuit and an exact matching circuit

the addresses of the memory cells in preparation for the memorization operation with the address of the commands that are in the instruction buffer; command recording circuit directly from the information buffer of the recording control device operative

memory in case of coincidence of the address of the memory cell into which the recording is made, with the address of any command stored in the command buffer of the command processor, simultaneously with writing to the memory cell; separate transmissions of read and write requests from the command processor to the main RAM management device, the switching circuit associated with the outputs of the command buffer registers, and its outputs through the command decoding circuit .y and the address modification circuit are connected to the inputs of the fast and accurate verification, the output of which is connected to the scheme of recording commands to the command buffer directly from the information

a write buffer, as well as a conflict analysis block associated with instruction decoding circuits and with schemes for analyzing the filling of magazines of onerations of processors for performing operations with fixed and floating

with a general release register signaling circuit, a signaling circuit availability scheme of the information storage buffer registers of the main memory management device

when sending a write request, the availability of buffer buffers for processors of execution of operations from a fixed) floating point, with registers of floating-point arithmetic and connected

control outputs to the switching circuit for transmitting commands for decoding, the circuit for generating commands for extra blocks, the circuit for modifying the address, stores for processors with fixed and

floating, the request creation scheme, to the main RAM management device.

2. The central processor of a multiprogram multiprocessor computing system according to claim 1, characterized in that, in order to expand the system of executable instructions, there is a switch connected to the command processor decoding circuit, the control inputs of which are connected to the collision analysis unit,

and exits - with input tires of the connected specialized processing unit.

3. The central processor of a multiprogram multiprocessor computing system according to claim. Characterized in that, for